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1990 – 1999
- 1995
[b1]Jörg Beichter:
Architektur eines programmierbaren neuronalen Signalprozessors in VLSI CMOS-Technologie zur Simulation komplexer künstlicher neuronaler Netze. Technical University of Berlin, Germany, 1995, pp. 1-148- [c2]Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Joachim Gläß, Andreas Wurz, Reinhard Männer:
SYNAPSE-1: a high-speed general purpose parallel neurocomputer system. IPPS 1995: 774-781 - 1993
- [j3]Ulrich Ramacher, Wolfgang Raab, Joachim K. Anlauf, J. A. Ulrich Hachmann, Jörg Beichter, Nico Brüls, Matthias Wesseling, Elisabeth Sicheneder, Reinhard Männer, Joachim Gläß, Andreas Wurz:
Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1. Int. J. Neural Syst. 4(4): 333-336 (1993) - [j2]Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar:
Design of a general-purpose neural signal processor. Neurocomputing 5(1): 17-23 (1993) - [j1]Ulrich Ramacher, Jörg Beichter, Nico Brüls:
A general-purpose signal processor architecture for neurocomputing and preprocessing applications. J. VLSI Signal Process. 6(1): 45-56 (1993) - [c1]Ulrich Ramacher, Jörg Beichter, Nico Brüls, Elisabeth Sicheneder:
Architecture and VLSI Design of a VLSI Neural Signal Processor. ISCAS 1993: 1975-1978
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