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2010 – 2019
- 2018
[c5]Mateja Putic, Swagath Venkataramani, Schuyler Eldridge
, Alper Buyuktosunoglu, Pradip Bose, Mircea Stan:
Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration. DAC 2018: 14:1-14:6- 2017
- [j2]Mateja Putic, A. J. Varshneya, Mircea R. Stan:
Hierarchical Temporal Memory on the Automata Processor. IEEE Micro 37(1): 52-59 (2017) - 2014
- [c4]Hang Zhang, Mateja Putic, John C. Lach:
Low Power GPGPU Computation with Imprecise Hardware. DAC 2014: 99:1-99:6 - 2013
- [c3]Matthew Weber, Mateja Putic, Hang Zhang, John C. Lach, Jiawei Huang:
Balancing Adder for error tolerant applications. ISCAS 2013: 3038-3041 - 2010
- [j1]Benton H. Calhoun, Joseph F. Ryan, Sudhanshu Khanna, Mateja Putic, John C. Lach:
Flexible Circuits and Architectures for Ultralow Power. Proc. IEEE 98(2): 267-282 (2010)
2000 – 2009
- 2009
- [c2]Mateja Putic, Liang Di, Benton H. Calhoun, John C. Lach:
Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design. ICCD 2009: 491-497 - 2008
- [c1]Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun:
Power switch characterization for fine-grained dynamic voltage scaling. ICCD 2008: 605-611
Coauthor Index
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