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2020 – today
- 2022
[c11]Yutaka Yamada, Keisuke Maeda, Takahiro Ogawa, Miki Haseyama:
Trend Prediction of Students' Mock Examination Results Using Matrix Completion. GCCE 2022: 891-892- 2020
- [j5]Yutaka Yamada
, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda:
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. IEEE J. Solid State Circuits 55(1): 120-132 (2020)
2010 – 2019
- 2019
- [c10]Yutaka Yamada, Takahiro Ogawa, Miki Haseyama:
Performance Prediction Method of Examinees Based on Matrix Completion. GCCE 2019: 229-230 - [c9]Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa:
A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. ISSCC 2019: 132-134 - 2015
- [c8]Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori:
18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. ISSCC 2015: 1-3 - 2011
- [j4]Toshiyuki Harada, Yoshiaki Nakagawa, Takehiko Ogura, Yutaka Yamada, Takehiro Ohe, Hisashi Miyagawa:
Virtual Screening for Ligands of the Insect Molting Hormone Receptor. J. Chem. Inf. Model. 51(2): 296-305 (2011) - [c7]Takashi Yoshikawa, Fumihiko Hyuga, Masayuki Tokunaga, Yutaka Yamada, Shigehiro Asano:
FlexGrip™: A small and high-performance programmable hardware for highly sequential application. COOL Chips 2011: 1-3
2000 – 2009
- 2009
- [j3]Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano:
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distributed Syst. 20(8): 1126-1141 (2009) - 2006
- [j2]Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano:
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distributed Syst. 17(12): 1425-1437 (2006) - [c6]Takashi Yoshikawa, Yutaka Yamada, Shigehiro Asano:
An implementation of hardware accelerator using dynamically reconfigurable architecture. Hot Chips Symposium 2006: 1-38 - 2005
- [j1]Nobuaki Kamimoto, Yutaka Yamada, Masami Kitamura, Kiyoshi Nishikawa:
Evaluation of vibration in many positions by SOM. Artif. Life Robotics 9(1): 7-11 (2005) - [c5]Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano:
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280 - 2004
- [c4]Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura:
Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC 2004: 301-311 - [c3]Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM 2004: 328-329 - [c2]Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima:
Stream applications on the dynamically reconfigurable processor. FPT 2004: 137-144 - [c1]Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS 2004
Coauthor Index
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