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2010 – 2019
- 2017
[j12]Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Emerg. Top. Comput. 5(2): 151-163 (2017)- 2016
- [c17]Masanori Natsui
, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS 2016: 1878-1881 - 2015
- [c16]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki:
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE 2015: 1006-1011 - [c15]Akira Mochizuki, Naoto Yube, Takahiro Hanyu:
Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor. IECON 2015: 3283-3288 - [c14]Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. NANOARCH 2015: 39-44 - [c13]Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC 2015: 172- - 2014
- [j11]Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express 11(3): 20131006 (2014) - [j10]Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11(10): 20140297 (2014) - [j9]Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11(13): 20140296 (2014) - [j8]Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. 97-D(6): 1546-1556 (2014) - [j7]Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu:
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. IEICE Trans. Inf. Syst. 97-D(9): 2304-2311 (2014) - [c12]Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu:
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. APCCAS 2014: 683-686 - [c11]Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu:
Energy-aware current-mode inter-chip link for a dependable GALS NoC platform. ISCAS 2014: 1865-1868 - [c10]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link. ISMVL 2014: 67-72 - 2013
- [j6]Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10(23): 20130772 (2013)
2000 – 2009
- 2007
- [j5]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Trans. Electron. 90-C(4): 683-691 (2007) - [c9]Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto:
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43 - [c8]Akira Mochizuki, Masatomo Miura, Takahiro Hanyu:
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ISMVL 2007: 57 - 2006
- [j4]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Trans. Electron. 89-C(11): 1591-1597 (2006) - [c7]Akira Mochizuki, Takahiro Hanyu:
Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ISMVL 2006: 5 - [c6]Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL 2006: 14 - 2005
- [j3]Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu:
TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(6): 1408-1415 (2005) - [j2]Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama:
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 481-497 (2005) - [c5]Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu:
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL 2005: 138-143 - 2004
- [c4]Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu:
Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ISMVL 2004: 192-197 - 2003
- [c3]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212
1990 – 1999
- 1995
- [c2]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64-71 - 1994
- [c1]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26 - 1992
- [j1]Masami Shinohara, Shinya Saida, Yutaka Shimizu, Akira Mochizuki, Kanehiro Sorimachi:
Three-Dimensional Tactile Display by Multi-Stage Actuator. J. Robotics Mechatronics 4(3): 231-236 (1992)
Coauthor Index
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