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ORCIDGraham Schelle
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2010 – 2019
- 2016
[c11]Graham Schelle:
Keynote 1 - Growing the ReConFig community through python, zynq and hardware overlays. ReConFig 2016: 1- 2010
- [c10]Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang:
Intel nehalem processor core made FPGA synthesizable. FPGA 2010: 3-12
2000 – 2009
- 2008
- [c9]Graham Schelle, Dirk Grunwald:
Exploring FPGA network on chip implementations across various application and network loads. FPL 2008: 41-46 - [c8]Aveek Dutta, Jeff Fifield, Graham Schelle, Dirk Grunwald, Douglas C. Sicker
:
An intelligent physical layer for cognitive radio networks. WICON 2008: 12 - 2007
- [c7]Graham Schelle, Dirk Grunwald:
Abstracting Modern FCCMs To Provide a Single Interface to Architectural Resources. FCCM 2007: 305-308 - [c6]Graham Schelle, Jeff Fifield, Dirk Grunwald:
A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects. FPL 2007: 177-182 - 2006
- [c5]David A. Penry, Daniel Fay, David Hodgdon, Ryan Wells, Graham Schelle, David I. August, Dan Connors:
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors. HPCA 2006: 29-40 - 2005
- [c4]Graham Schelle, Dirk Grunwald:
CUSP: a modular framework for high speed network applications on FPGAs. FPGA 2005: 246-257 - 2004
- [c3]Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle:
Mapping a domain specific language to a platform FPGA. DAC 2004: 924-927 - [c2]Graham Schelle, Dirk Grunwald:
Automated Speculation and Parallelism in High Performance Network Applications. FPL 2004: 1175 - 2003
- [c1]Marco Gruteser, Graham Schelle, Ashish Jain, Richard Han, Dirk Grunwald:
Privacy-Aware Location Sensor Networks. HotOS 2003: 163-168
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