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2020 – today
- 2024
[c4]Suman Datta, E. Sarkar, Khandker Akif Aabrar, Shan Deng, J. Shin, Arijit Raychowdhury, Shimeng Yu, Asif Khan:
Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits. VLSI Technology and Circuits 2024: 1-2- [c3]H. Fukutome, J. Kim, J. Shin, J. Kim, Y. Lee, Y. Park, D. Oh, S. Chae, B. Eom, YS Nam, M. Lee, S. Ha, EG Chung, J. Kim, M. Jo, SH Lee, S. Kim, KH Cho, KW Lee, DW Kim, HJ Cho, K. Rim, SD Kwon, J. Song:
Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2nm Node. VLSI Technology and Circuits 2024: 1-2
2010 – 2019
- 2018
- [c2]F. Griggio, James Palmer, F. Pan, N. Toledo, Anthony Schmitz, Ilan Tsameret, R. Kasim, Gerald S. Leatherman, Jeffery Hicks, A. Madhavan, J. Shin, J. Steigerwald, A. Yeoh, C. Auth:
Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology. IRPS 2018: 6 - 2013
- [j2]A. B. Dieker, J. Shin:
From Local to Global Stability in Stochastic Processing Networks Through Quadratic Lyapunov Functions. Math. Oper. Res. 38(4): 638-664 (2013) - 2011
- [j1]Hooman Darabi, Paul Chang, Henrik Jensen, Alireza Zolfaghari, Paul Lettieri, John C. Leete, Behnam Mohammadi, Janice Chiu, Qiang (Tom) Li, Shr-Lung Chen, Zhimin Zhou, Morteza Vadipour, C. Chen, Yuyu Chang, Ahmad Mirzaei, Ahmad Yazdi, Mohammad Nariman, Amir Hadji-Abdolhamid, Ethan Chang, Barry Zhao, Kevin Juan, Puneet Suri, Claire Guan, Louie Serrano, John Leung, J. Shin, Jay Kim, Huey Tran, Patrick Kilcoyne, H. Vinh, Eric Raith, M. Koscal, Ajat Hukkoo, C. Hayek, V. Rakhshani, Charlie Wilcoxson, Maryam Rofougaran, Ahmadreza Rofougaran:
A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS. IEEE J. Solid State Circuits 46(4): 870-882 (2011)
2000 – 2009
- 2007
- [c1]W. Chang, J. Shin:
Modified Dynamic Time Warping for Stroke-Based On-line Signature Verification. ICDAR 2007: 724-728
Coauthor Index
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