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ORCIDHamid Reza Pourshaghaghi
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2020 – today
- 2023
[j6]Mahsa Mousavi, Hamid Reza Pourshaghaghi, Akash Kumar
, Henk Corporaal:
MTTR reduction of FPGA scrubbing: Exploring SEU sensitivity. Microprocess. Microsystems 101: 104841 (2023)- 2020
- [j5]Mark Wijtvliet, Bjarni Pont, Christiaan Brinkerink, Hamid Reza Pourshaghaghi, Roel Jordans, Jörg Hörandel, Jochem Beurskens, Ronald Bouma, Joris Dalderup, Peter Dolron, Jeroen Gubbels, Veronica Marcela Gomez Medina, Louis D. van Harten, Thijn Hermsen, Ivar Jansen, Daan Kapitein, Martijn Koedam, Ronis T. Maximidis, Kristiaan Zoontjens:
PR3: A system For radio-interferometry and radiation measurement on sounding rockets. Microprocess. Microsystems 77: 103163 (2020) - [j4]Dip Goswami, Hamid Reza Pourshaghaghi:
Special issue on cyber-physical systems design and applications related to DSD2018. Microprocess. Microsystems 78: 103236 (2020)
2010 – 2019
- 2019
- [c8]Mahsa Mousavi, Hamid Reza Pourshaghaghi, Henk Corporaal, Akash Kumar:
Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory. DFT 2019: 1-6 - [c7]Mahsa Mousavi, Sayandip De, Hamid Reza Pourshaghaghi, Henk Corporaal:
Fault Tolerant FPGAs: Where to Spend the Effort? DSD 2019: 651-654 - 2018
- [j3]Louis D. van Harten, Mahsa Mousavi, Roel Jordans, Hamid Reza Pourshaghaghi:
Determining the necessity of fault tolerance techniques in FPGA devices for space missions. Microprocess. Microsystems 63: 1-10 (2018) - [c6]Mahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Roel Jordans, Henk Corporaal:
A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA. DSD 2018: 221-228 - 2017
- [c5]Louis D. van Harten, Roel Jordans, Hamid Reza Pourshaghaghi:
Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case Study. DSD 2017: 299-306 - 2013
- [j2]Hamid Reza Pourshaghaghi, José Pineda de Gyvez:
Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking. IEEE Trans. Computers 62(12): 2397-2410 (2013) - 2012
- [c4]Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez:
Sliding-Mode Control to Compensate PVT Variations in dual core systems. DATE 2012: 1048-1053 - 2011
- [c3]Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, José Pineda de Gyvez:
Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage. DSD 2011: 135-139 - 2010
- [j1]Hamid Reza Pourshaghaghi, Reza Ahmadi, Mohammad Reza Jahed-Motlagh, Behnam Kia:
Experimental Realization of a Reconfigurable Three Input, One Output Logic Function Based on a Chaotic Circuit. Int. J. Bifurc. Chaos 20(3): 715-726 (2010) - [c2]Hamid Reza Pourshaghaghi, José Pineda de Gyvez:
Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling. ICECS 2010: 281-284
2000 – 2009
- 2009
- [c1]Hamid Reza Pourshaghaghi, José Pineda de Gyvez:
Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller. ICECS 2009: 779-782
Coauthor Index
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