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ORCIDSiva Sankar Yellampalli
Person information
- affiliation: SRM University-AP, Department of Electronics and Communication Engineering, Amaravati, India
- affiliation: Visvesvaraya Technological University Extension Center (VTU), Bangalore, India
- affiliation (former): Lousiana State University, Baton Rouge, LA, USA
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2020 – today
- 2024
[j8]Rahul Gowtham Poola
, P. L. Lahari, Siva Sankar Yellampalli:
SyntDiaNet: Integrating feature extraction, transfer learning and classifier-embedded generative adversarial network for advanced pneumonia diagnosis. Multim. Tools Appl. 83(27): 70217-70255 (2024)- [c14]Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Aditya Japa, Sushma Nirmala Sambatur, Chongyan Gu, Siva Sankar Yellampalli, Ramesh Vaddi:
Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices. ISCAS 2024: 1-5 - 2023
- [j7]Gayathri Lakshmi, V. Udaya Sankar, Y. Siva Sankar:
A Survey of PCB Defect Detection Algorithms. J. Electron. Test. 39(5): 541-554 (2023) - [j6]Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi:
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. Microelectron. J. 133: 105711 (2023) - [j5]Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi:
A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks. Microelectron. J. 139: 105867 (2023) - 2022
- [j4]V. Udaya Sankar, Gayathri Lakshmi, Y. Siva Sankar:
A Review of Various Defects in PCB. J. Electron. Test. 38(5): 481-491 (2022) - [j3]Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi:
Negative capacitance FETs for energy efficient and hardware secure logic designs. Microelectron. J. 119: 105320 (2022) - [c13]Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi:
Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks. iSES 2022: 321-325 - 2021
- [c12]Sameeksha Konakalla, Lakshmi Vyshnavi Kunchala, Siva Sankar Yellampalli:
Smart Agriculture using IoT & Filtering Technology. ICCCNT 2021: 1-5 - [c11]P. L. Lahari, Siva Sankar Yellampalli, Ramesh Vaddi:
Systolic Array based Multiply Accumulation Unit for IoT Edge Accelerators. iSES 2021: 220-223 - [c10]Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi:
Steep Switching NCFET based Logic for Future Energy Efficient Electronics. iSES 2021: 327-330 - [c9]Parshal Chitrakar, Yoganand Biradavolu, Siva Sankar Yellampalli:
GPS and LoRa module Based Safety Alert system. RFID-TA 2021: 256-259
2010 – 2019
- 2019
- [j2]Nanda Kishora Holla, Siva Sankar Yellampalli:
Smart Receivers with Modular and Multifunctional Front-End Blocks: The Benefits of Using Programmable Modulators and Demodulators. IEEE Consumer Electron. Mag. 8(1): 61-65 (2019) - 2015
- [c8]Prakruthi T. G., Siva Sankar Yellampalli:
Design and implementation of sample and hold circuit in 180nm CMOS technology. ICACCI 2015: 1148-1151 - [c7]M. R. Gowthami, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli:
Modified low power scan based technique. VDAT 2015: 1-5 - [c6]N. Ravi Kiran, G. Harish, A. Karthik, Siva Sankar Yellampalli:
Low power and hardware cost STUMPS BIST. VDAT 2015: 1-4 - [c5]Munishamanna Rithesh, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli:
Detection and analysis of hardware trojan using scan chain method. VDAT 2015: 1-6 - [c4]Favoureen Swer, V. Pradeep, Siva Sankar Yellampalli:
Analog BIST for Capacitive MEMS Sensor using PLL. WCI 2015: 348-352 - 2014
- [c3]Dwaraka N. Oruganti, Siva Sankar Yellampalli:
Design of power efficient SPI interface. ICACCI 2014: 2602-2606 - [c2]P. Kavyashree, Siva Sankar Yellampalli:
The Design of Ultra Low Power CMOS CGLNA in Nanometer Technology. ISED 2014: 15-19 - 2011
- [j1]Rajiv Soundararajan, Ashok Srivastava, Siva Sankar Yellampalli:
ΔIDDQ Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects. Circuits Syst. 2(3): 133-138 (2011)
2000 – 2009
- 2003
- [c1]Jong-Kook Kim, Sameer Shivle, Howard Jay Siegel, Anthony A. Maciejewski, Tracy D. Braun, Myron Schneider, Sonja Tideman, Ramakrishna Chitta, Raheleh B. Dilmaghani, Rohit Joshi, Aditya Kaul, Ashish Sharma, Siddhartha Sripada, Praveen Vangari, Siva Sankar Yellampalli:
Dynamic Mapping in a Heterogeneous Environment with Tasks Having Priorities and Multiple Deadlines. IPDPS 2003: 98
Coauthor Index
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last updated on 2024-08-03 20:12 CEST by the dblp team
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