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2020 – today
- 2024
[j133]Satoru Jimbo
, Tatsuhiko Shirai, Nozomu Togawa, Masato Motomura, Kazushi Kawamura:
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization. IEEE Access 12: 43660-43673 (2024)- [j132]Sora Tomita, Tatsuhiko Shirai, Nozomu Togawa:
Ising Machine Approach to the Lecturer-Student Assignment Problem. IEEE Access 12: 49752-49761 (2024) - [j131]Kentaro Ohno, Tatsuhiko Shirai, Nozomu Togawa:
Toward Practical Benchmarks of Ising Machines: A Case Study on the Quadratic Knapsack Problem. IEEE Access 12: 97678-97690 (2024) - [j130]Akihisa Okada, Keisuke Otaki, Tadayoshi Matsumori, Hiroaki Yoshida, Kotaro Terada, Nozomu Togawa:
QUBO Formulation Using Sequence Pair With Search Space Restriction for Rectangle Packing Problem. IEEE Access 12: 156627-156638 (2024) - [j129]Soma Kawakami, Yosuke Mukasa, Siya Bao, Dema Ba, Junya Arai, Satoshi Yagi, Junji Teramoto, Nozomu Togawa:
Ising-Machine-Based Solver for Constrained Graph Coloring Problems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1): 38-51 (2024) - [j128]Soma Kawakami, Kentaro Ohno, Dema Ba, Satoshi Yagi, Junji Teramoto, Nozomu Togawa:
Giving a Quasi-Initial Solution to Ising Machines by Controlling External Magnetic Field Coefficients. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1): 52-62 (2024) - [j127]Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa:
Hardware-Trojan Detection at Gate-Level Netlists Using a Gradient Boosting Decision Tree Model and Its Extension Using Trojan Probability Propagation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1): 63-74 (2024) - [j126]Kota Hisafuru, Kazunari Takasaki, Nozomu Togawa:
An Anomalous Behavior Detection Method Utilizing IoT Power Waveform Shapes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1): 75-86 (2024) - [j125]Nozomu Togawa:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 530 (2024) - [j124]Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa:
An Ising-Machine-Based Solver of Vehicle Routing Problem With Balanced Pick-Up. IEEE Trans. Consumer Electron. 70(1): 445-459 (2024) - [c185]Keisuke Fukada, Tatshuhiko Shirai, Nozomu Togawa:
Hybrid Iterative Annealing Method Using a Quantum Annealer and a Classical Computer. ICCE 2024: 1-6 - [c184]Kota Hisafuru, Nozomu Togawa:
Gen-Power: Anomaly Detection in IoT Devices Utilizing Generated Power Waveforms. ICCE 2024: 1-6 - [c183]Dai Kajimoto, Etsushi Saeki, Siya Bao, Nozomu Togawa:
Carrying-Mode-Free Stair Ascent and Descent Estimation using Smartphones. ICCE 2024: 1-6 - [c182]Soma Kawakami, Kentaro Ohno, Dema Ba, Satoshi Yagi, Junji Teramoto, Nozomu Togawa:
An Interaction Coefficient Control Method for Setting Initial Solutions to Ising Machines. ICCE 2024: 1-2 - [c181]Ryotaro Negishi, Nozomu Togawa:
Evaluation of Ensemble Learning Models for Hardware-Trojan Identification at Gate-level Netlists. ICCE 2024: 1-6 - [c180]Etsushi Saeki, Siya Bao, Toshinori Takayama, Nozomu Togawa:
Time-Dependent Multi-Objective Trip Planning by Ant Colony Optimization with Route API. ICCE 2024: 1-2 - [c179]Yui Tsuyumine, Kenichi Masuda, Takeshi Hachikawa, Tsuyoshi Haga, Yuta Yachi, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa:
Optimization of Practical Time-Dependent Vehicle Routing Problem by Ising Machines. ICCE 2024: 1-5 - [c178]Ryusei Eda, Kota Hisafuru, Nozomu Togawa:
Anomalous IoT Behavior Detection by Generated Power Waveforms with Hyper-parameter Tuning. IOLTS 2024: 1-3 - [c177]Hibiki Nakanishi, Kota Hisafuru, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa:
Initial Seeds Generation Using LLM for IoT Device Fuzzing. IOTSMS 2024: 5-10 - [c176]Yuka Ikegami, Ryotaro Negishi, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa:
Prioritizing Vulnerability Assessment Items Using LLM Based on IoT Device Documentations. IOTSMS 2024: 147-152 - [c175]Yuta Atobe, Masashi Tawada, Nozomu Togawa:
A Novel Classical-Ising Hybrid Annealing Method with QUBO Model Cutting. MWSCAS 2024: 1154-1157 - [c174]Tatsuya Noguchi, Keisuke Fukada, Siya Bao, Nozomu Togawa:
Multi-Day Intermodal Trip Planning Using subQUBO Annealing with Correction Processing. QCE 2024: 380-381 - [c173]Yuta Yachi, Masashi Tawada, Nozomu Togawa:
QUBO Coefficient Dynamic Ratio Shrinking Method for Quantum Annealers. QCE 2024: 384-385 - [c172]Sora Tomita, Tatsuhiko Shirai, Nozomu Togawa:
Variable Reduction Method for Quadratic Three-Dimensional Assignment Problem with FMQA. QCE 2024: 404-405 - [c171]Chihiro Dogo, Kazuhiro Saito, Nozomu Togawa:
Optimization of Base Station Power Supply Selection by Quantum Annealing. QCE 2024: 408-409 - [c170]Kinya Iwata, Masashi Tawada, Nozomu Togawa:
Non-zero Coefficients Removing Method to Improve the Ising Machine Solving Performance. QCE 2024: 428-429 - [c169]Takeru Ota, Keisuke Fukada, Nozomu Togawa:
Personalized Course Selection Optimization Using an Ising Machine. QCE 2024: 430-431 - [c168]Keisuke Fukada, Tatsuhiko Shirai, Mikio Morita, Yoshinori Tomita, Koichi Kimura, Nozomu Togawa:
Large-Sized VQE Performance Profiling in Quantum Chemistry Using a Multi-Node Quantum Simulator. QCE 2024: 432-433 - [i6]Kentaro Ohno, Tatsuhiko Shirai, Nozomu Togawa:
Toward Practical Benchmarks of Ising Machines: A Case Study on the Quadratic Knapsack Problem. CoRR abs/2403.19175 (2024) - 2023
- [j123]Shuta Kikuchi, Nozomu Togawa, Shu Tanaka:
Dynamical Process of a Bit-Width Reduced Ising Model With Simulated Annealing. IEEE Access 11: 95493-95506 (2023) - [j122]Tatsuya Noguchi, Keisuke Fukada, Siya Bao, Nozomu Togawa:
Trip Planning Based on subQUBO Annealing. IEEE Access 11: 100383-100395 (2023) - [j121]Bo Wei, Hang Song, Makoto Nakamura, Koichi Kimura, Nozomu Togawa, Jiro Katto:
QuDASH: Quantum-Inspired Rate Adaptation Approach for DASH Video Streaming. IEEE Access 11: 118462-118473 (2023) - [j120]Yuta Yachi, Masashi Tawada, Nozomu Togawa:
An Efficient Combined Bit-Width Reducing Method for Ising Models. IEICE Trans. Inf. Syst. 106(4): 495-508 (2023) - [j119]Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa:
R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training. IEEE Trans. Computers 72(2): 333-345 (2023) - [j118]Tatsuhiko Shirai, Nozomu Togawa:
Multi-Spin-Flip Engineering in an Ising Machine. IEEE Trans. Computers 72(3): 759-771 (2023) - [j117]Tatsuhiko Shirai, Nozomu Togawa:
Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines. IEEE Trans. Computers 72(8): 2151-2164 (2023) - [c167]Soma Kawakami, Yosuke Mukasa, Siya Bao, Dema Ba, Junya Arai, Satoshi Yagi, Junji Teramoto, Nozomu Togawa:
A Constrained Graph Coloring Solver Based on Ising Machines. ICCE 2023: 1-6 - [c166]Soma Kawakami, Kentaro Ohno, Dema Ba, Satoshi Yagi, Junji Teramoto, Nozomu Togawa:
A Quasi-Initial Solution Giving Method for Ising Machines by Controlling External Magnetic Field Coefficients. ICCE 2023: 1-6 - [c165]Matthieu Parizy, Norihiro Kakuko, Nozomu Togawa:
Fast Hyperparameter Tuning for Ising Machines. ICCE 2023: 1-6 - [c164]Dai Sato, Nozomu Togawa:
Fast and Accurate Smartglass Angles Inference Based on Periodic Behavior in Walking. ICCE 2023: 1-6 - [c163]Siya Bao, Nozomu Togawa:
Multi-Day Intermodal Travel Planning for Urban Cities Using Ising Machines. ITSC 2023: 54-60 - [c162]Yuta Yachi, Masashi Tawada, Nozomu Togawa:
A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output. SOCC 2023: 1-6 - [c161]Kento Hasegawa, Kazuki Yamashita, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa:
Membership Inference Attacks against GNN-based Hardware Trojan Detection. TrustCom 2023: 1222-1229 - [i5]Kentaro Ohno, Nozomu Togawa:
Linearization via Ordering Variables in Binary Optimization for Ising Machines. CoRR abs/2307.05125 (2023) - 2022
- [j116]Etsushi Saeki, Siya Bao, Toshinori Takayama, Nozomu Togawa:
Multi-Objective Trip Planning Based on Ant Colony Optimization Utilizing Trip Records. IEEE Access 10: 127825-127844 (2022) - [j115]Tatsuki Kurihara, Nozomu Togawa:
Hardware-Trojan Detection Based on the Structural Features of Trojan Circuits Using Random Forests. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(7): 1049-1060 (2022) - [j114]Tomoya Wakaizumi, Nozomu Togawa:
Carrying-mode Free Indoor Positioning Using Smartphone and Smartwatch and Its Evaluations. J. Inf. Process. 30: 52-65 (2022) - [j113]Daisuke Oku, Masashi Tawada, Shu Tanaka, Nozomu Togawa:
How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins. IEEE Trans. Computers 71(1): 223-234 (2022) - [j112]Yuta Atobe, Masashi Tawada, Nozomu Togawa:
Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances. IEEE Trans. Computers 71(10): 2606-2619 (2022) - [c160]Kota Hisafuru, Ryotaro Negishi, Soma Kawakami, Dai Sato, Kazuki Yamashita, Keisuke Fukada, Nozomu Togawa:
Autonomous driving system with feature extraction using a binarized autoencoder. FPT 2022: 1-4 - [c159]Ryotaro Negishi, Tatsuki Kurihara, Nozomu Togawa:
Hardware-Trojan Detection at Gate-level Netlists using Gradient Boosting Decision Tree Models. ICCE-Berlin 2022: 1-6 - [c158]Dai Sato, Nozomu Togawa:
A PDR Method Using Smartglasses Reducing Accumulated Errors by Detecting User's Stop Motions. ICCE 2022: 1-2 - [c157]Yuta Yachi, Yousuke Mukasa, Masashi Tawada, Nozomu Togawa:
Efficient Coefficient Bit-Width Reduction Method for Ising Machines. ICCE 2022: 1-6 - [c156]Tomokazu Yoshimura, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa:
QUBO Matrix Distorting Method for Consumer Applications. ICCE 2022: 1-6 - [c155]Kota Hisafuru, Kazunari Takasaki, Nozomu Togawa:
An Anomalous Behavior Detection Method for IoT Devices Based on Power Waveform Shapes. IOLTS 2022: 1-7 - [c154]Kazuki Yamashita, Tomohiro Kato, Kento Hasegawa, Seira Hidano, Kazuhide Fukushima, Nozomu Togawa:
Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists. IOLTS 2022: 1-7 - [c153]Matthieu Parizy, Przemyslaw Sadowski, Nozomu Togawa:
Cardinality Constrained Portfolio Optimization on an Ising Machine. SOCC 2022: 1-6 - [i4]Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa:
R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training. CoRR abs/2205.13702 (2022) - [i3]Bo Wei, Hang Song, Makoto Nakamura, Koichi Kimura, Nozomu Togawa, Jiro Katto:
QuDASH: Quantum-inspired rate adaptation approach for DASH video streaming. CoRR abs/2206.09427 (2022) - [i2]Matthieu Parizy, Norihiro Kakuko, Nozomu Togawa:
Fast Hyperparameter Tuning for Ising Machines. CoRR abs/2211.15869 (2022) - 2021
- [j111]Kensuke Tamura, Tatsuhiko Shirai, Hosho Katsura, Shu Tanaka, Nozomu Togawa:
Performance Comparison of Typical Binary-Integer Encodings in an Ising Machine. IEEE Access 9: 81032-81039 (2021) - [j110]Keisuke Fukada, Matthieu Parizy, Yoshinori Tomita, Nozomu Togawa:
A Three-Stage Annealing Method Solving Slot-Placement Problems Using an Ising Machine. IEEE Access 9: 134413-134426 (2021) - [j109]Kento Hasegawa, Tomotaka Inoue, Nozomu Togawa:
A Two-Stage Hardware Trojan Detection Method Considering the Trojan Probability of Neighbor Nets. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1516-1525 (2021) - [j108]Matthieu Parizy, Nozomu Togawa:
Analysis and Acceleration of the Quadratic Knapsack Problem on an Ising Machine. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1526-1535 (2021) - [j107]Kazunari Takasaki, Ryoichi Kida, Nozomu Togawa:
An Anomalous Behavior Detection Method Utilizing Extracted Application-Specific Power Behaviors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1555-1565 (2021) - [j106]Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Nozomu Togawa:
Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations. IEICE Trans. Inf. Syst. 104-D(2): 226-236 (2021) - [j105]Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa:
Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine. IEICE Trans. Inf. Syst. 104-D(4): 481-489 (2021) - [j104]Yosuke Mukasa, Tomoya Wakaizumi, Shu Tanaka, Nozomu Togawa:
An Ising Machine-Based Solver for Visiting-Route Recommendation Problems in Amusement Parks. IEICE Trans. Inf. Syst. 104-D(10): 1592-1600 (2021) - [j103]Yosuke Mukasa, Shu Tanaka, Nozomu Togawa:
Experimental Evaluations of Parallel Tempering on an Ising Machine. IPSJ Trans. Syst. LSI Des. Methodol. 14: 27-29 (2021) - [j102]Yuta Ishizaki, Yurie Koyama, Toshinori Takayama, Nozomu Togawa:
A Route Recommendation Method Considering Individual User's Preferences by Monte-Carlo Tree Search and Its Evaluations. J. Inf. Process. 29: 81-92 (2021) - [j101]Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa:
Generating Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. J. Inf. Process. 29: 236-246 (2021) - [c152]Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Nozomu Togawa:
Toward Learning Robust Detectors from Imbalanced Datasets Leveraging Weighted Adversarial Training. CANS 2021: 392-411 - [c151]Kazunari Takasaki, Kota Hisafuru, Ryotaro Negishi, Kazuki Yamashita, Keisuke Fukada, Tomoya Wakaizumi, Nozomu Togawa:
An autonomous driving system utilizing image processing accelerated by FPGA. FPT 2021: 1-4 - [c150]Tomoya Wakaizumi, Nozomu Togawa:
A PDR Method Combining Smartphone and Smartwatch based on Multi-Scenario Map Matching. GCCE 2021: 308-309 - [c149]Shota Matsuno, Masashi Tawada, Nozomu Togawa:
Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. ICCE 2021: 1-6 - [c148]Yosuke Mukasa, Tomoya Wakaizumi, Shu Tanaka, Nozomu Togawa:
Visiting-Route Recommendation in Amusement Parks and its Evaluations by an Ising Machine. ICCE 2021: 1-6 - [c147]Tomoya Wakaizumi, Nozomu Togawa:
An Indoor Positioning Method using Smartphone and Smartwatch Independent of Carrying Modes. ICCE 2021: 1-6 - [c146]Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa:
Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists. IOLTS 2021: 1-4 - [c145]Tatsuki Kurihara, Nozomu Togawa:
Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests. IOLTS 2021: 1-4 - [c144]Kazunari Takasaki, Ryoichi Kida, Nozomu Togawa:
An Anomalous Behavior Detection Method Based on Power Analysis Utilizing Steady State Power Waveform Predicted by LSTM. IOLTS 2021: 1-7 - [c143]Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa:
Multi-day Travel Planning Using Ising Machines for Real-world Applications. ITSC 2021: 3704-3709 - [c142]Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa:
An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines. VLSI-DAT 2021: 1-4 - [i1]Kento Hasegawa, Kazuki Yamashita, Seira Hidano, Kazuhide Fukushima, Kazuo Hashimoto, Nozomu Togawa:
Node-wise Hardware Trojan Detection Based on Graph Learning. CoRR abs/2112.02213 (2021) - 2020
- [j100]Tatsuhiko Shirai, Shu Tanaka, Nozomu Togawa:
Guiding Principle for Minor-Embedding in Simulated-Annealing-Based Ising Machines. IEEE Access 8: 210490-210502 (2020) - [j99]Makoto Nishizawa, Kento Hasegawa, Nozomu Togawa:
A Capacitance Measurement Device for Running Hardware Devices and Its Evaluations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(9): 1018-1027 (2020) - [j98]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures. IEICE Trans. Inf. Syst. 103-D(7): 1618-1622 (2020) - [j97]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. 13: 10-20 (2020) - [c141]Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa:
FPGA-based Heterogeneous Solver for Three-Dimensional Routing. ASP-DAC 2020: 11-12 - [c140]Shu Tanaka, Yoshiki Matsuda, Nozomu Togawa:
Theory of Ising Machines and a Common Software Platform for Ising Machines. ASP-DAC 2020: 659-666 - [c139]Masashi Tawada, Shu Tanaka, Nozomu Togawa:
A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines. ICCE 2020: 1-6 - [c138]Tatsuki Kurihara, Kento Hasegawa, Nozomu Togawa:
Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods. IOLTS 2020: 1-4 - [c137]Kazunari Takasaki, Kento Hasegawa, Ryoichi Kida, Nozomu Togawa:
An Anomalous Behavior Detection Method for IoT Devices by Extracting Application-Specific Power Behaviors. IOLTS 2020: 1-4 - [c136]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. LASCAS 2020: 1-4 - [c135]Masashi Tawada, Nozomu Togawa:
Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function. NEWCAS 2020: 271-274 - [c134]Siya Bao, Nozomu Togawa:
Document-Level Sentiment Classification in Japanese by Stem-Based Segmentation with Category and Data-Source Information. ICSC 2020: 311-314
2010 – 2019
- 2019
- [j96]Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(4): 641-653 (2019) - [j95]Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(6): 860-865 (2019) - [j94]Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(8): 953-965 (2019) - [j93]Daisuke Oku, Kotaro Terada, Masato Hayashi, Masanao Yamaoka, Shu Tanaka, Nozomu Togawa:
A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines. IEICE Trans. Inf. Syst. 102-D(9): 1696-1706 (2019) - [j92]Nozomu Togawa:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 12: 1 (2019) - [j91]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
An FPGA Implementation Method based on Distributed-register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12: 38-41 (2019) - [c133]Siya Bao, Masao Yanagisawa, Nozomu Togawa:
A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments. ICIS (best papers) 2019: 109-123 - [c132]Kohei Nozawa, Kento Hasegawa, Seira Hidano, Shinsaku Kiyomoto, Kazuo Hashimoto, Nozomu Togawa:
Adversarial Examples for Hardware-Trojan Detection at Gate-Level Netlists. CyberICPS/SECPRE/SPOSE/ADIoT@ESORICS 2019: 341-359 - [c131]Kota Takehara, Daisuke Oku, Yoshiki Matsuda, Shu Tanaka, Nozomu Togawa:
A Multiple Coefficients Trial Method to Solve Combinatorial Optimization Problems for Simulated-annealing-based Ising Machines. ICCE-Berlin 2019: 64-69 - [c130]Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Hidetoshi Matsuoka, Kaoru Kawamura, Nozomu Togawa:
Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine. ICCE-Berlin 2019: 221-226 - [c129]Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa:
Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines. ICCE-Berlin 2019: 227-232 - [c128]Yuta Ishizaki, Toshinori Takayama, Nozomu Togawa:
A Route Recommendation Method Based on Personal Preferences by Monte-Carlo Tree Search. ICCE-Berlin 2019: 404-409 - [c127]Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE 2019: 1-6 - [c126]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. ICECS 2019: 578-581 - [c125]Kento Hasegawa, Kazunari Takasaki, Makoto Nishizawa, Ryota Ishikawa, Kazushi Kawamura, Nozomu Togawa:
Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board. FPT 2019: 457-460 - [c124]Kento Hasegawa, Kiyoshi Chikamatsu, Nozomu Togawa:
Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis. IOLTS 2019: 54-57 - [c123]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Error Correction Coding of Stochastic Numbers Using BER Measurement. IOLTS 2019: 243-246 - [c122]Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. ISCAS 2019: 1-4 - [c121]Yuta Ideguchi, Norifumi Kamiya, Masashi Tawada, Nozomu Togawa:
Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder. MWSCAS 2019: 981-984 - 2018
- [j90]Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(5): 831-843 (2018) - [j89]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1002-1013 (2018) - [j88]Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1014-1024 (2018) - [j87]Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1025-1034 (2018) - [j86]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1045-1052 (2018) - [j85]Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2308-2319 (2018) - [j84]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2320-2326 (2018) - [j83]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - [j82]Nozomu Togawa:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - [c120]Makoto Nishizawa, Kento Hasegawa, Nozomu Togawa:
Capacitance Measurement of Running Hardware Devices and its Application to Malicious Modification Detection. APCCAS 2018: 362-365 - [c119]Siya Bao, Masao Yanagisawa, Nozomu Togawa:
Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis. IEEE BigData 2018: 3628-3637 - [c118]Tomotaka Inoue, Kento Hasegawa, Yuki Kobayashi, Masao Yanagisawa, Nozomu Togawa:
Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach. ICCE-Berlin 2018: 1-4 - [c117]Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information. ICCE-Berlin 2018: 1-4 - [c116]Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests. ICCE-Berlin 2018: 1-2 - [c115]Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
Bicycle Behavior Recognition using Sensors Equipped with Smartphone. ICCE-Berlin 2018: 1-6 - [c114]Siya Bao, Masao Yanagisawa, Nozomu Togawa:
Road-illuminance level inference across road networks based on Bayesian analysis. ICCE 2018: 1-6 - [c113]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
A hardware-Trojan classification method utilizing boundary net structures. ICCE 2018: 1-4 - [c112]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. IOLTS 2018: 53-56 - [c111]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. IOLTS 2018: 97-102 - [c110]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. ISCAS 2018: 1-5 - [c109]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A loop structure optimization targeting high-level synthesis of fast number theoretic transform. ISQED 2018: 106-111 - [c108]Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. NGCAS 2018: 182-185 - [c107]Kento Hasegawa, Youhua Shi, Nozomu Togawa:
Hardware Trojan Detection Utilizing Machine Learning Approaches. TrustCom/BigDataSE 2018: 1891-1896 - [c106]Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
An Ising model mapping to solve rectangle packing problem. VLSI-DAT 2018: 1-4 - 2017
- [j81]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa:
Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(4): 1015-1028 (2017) - [j80]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1427-1438 (2017) - [j79]Koki Igawa, Masao Yanagisawa, Nozomu Togawa:
A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1439-1451 (2017) - [j78]Siya Bao, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa:
A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(11): 2439-2450 (2017) - [j77]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2857-2868 (2017) - [j76]Kotaro Terada, Masao Yanagisawa, Nozomu Togawa:
A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2911-2924 (2017) - [j75]Nozomu Togawa:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 10: 1 (2017) - [c105]Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Soft error tolerant latch designs with low power consumption (invited paper). ASICON 2017: 52-55 - [c104]Daiki Asai, Masao Yanagisawa, Nozomu Togawa:
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. ASICON 2017: 64-67 - [c103]Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
A low cost and high speed CSD-based symmetric transpose block FIR implementation. ASICON 2017: 311-314 - [c102]Tomotaka Inoue, Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Designing hardware trojans and their detection based on a SVM-based approach. ASICON 2017: 811-814 - [c101]Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa:
A stayed location estimation method for sparse GPS positioning information. GCCE 2017: 1-5 - [c100]Ryoya Momose, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa:
An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons. GCCE 2017: 1-5 - [c99]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
A robust scan-based side-channel attack method against HMAC-SHA-256 circuits. ICCE-Berlin 2017: 79-84 - [c98]Siya Bao, Masao Yanagisawa, Nozomu Togawa:
Personalized one-day travel with multi-nearby-landmark recommendation. ICCE-Berlin 2017: 239-242 - [c97]Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojan detection and classification based on steady state learning. IOLTS 2017: 215-220 - [c96]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojans classification for gate-level netlists using multi-layer neural networks. IOLTS 2017: 227-232 - [c95]Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa:
Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. ISCAS 2017: 1-4 - [c94]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
Effective write-reduction method for MLC non-volatile memory. ISCAS 2017: 1-4 - [c93]Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A selector-based FFT processor and its FPGA implementation. ISOCC 2017: 88-89 - [c92]Yuki Yahagi, Masao Yanagisawa, Nozomu Togawa:
Robust AES circuit design for delay variation using suspicious timing error prediction. ISOCC 2017: 101-102 - 2016
- [j74]Koki Igawa, Masao Yanagisawa, Nozomu Togawa:
Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms. IEICE Electron. Express 13(18): 20160641 (2016) - [j73]Koki Igawa, Masao Yanagisawa, Nozomu Togawa:
A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1278-1293 (2016) - [j72]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1294-1310 (2016) - [j71]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa:
Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1410-1414 (2016) - [j70]Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa:
Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2335-2347 (2016) - [j69]Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa:
A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2348-2362 (2016) - [j68]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2398-2411 (2016) - [j67]Nozomu Togawa:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 9: 1 (2016) - [c91]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
Implementation evaluation of scan-based attack against a Trivium cipher circuit. APCCAS 2016: 220-223 - [c90]Siya Bao, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa:
A safe and comprehensive route finding method for pedestrian based on lighting and landmark. GCCE 2016: 1-5 - [c89]Keisuke Kono, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa:
Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning. GCCE 2016: 1-2 - [c88]Ryoya Yano, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa:
Pedestrian navigation based on landmark recognition using glass-type wearable devices. GCCE 2016: 1-2 - [c87]Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Hardware Trojans classification for gate-level netlists based on machine learning. IOLTS 2016: 203-206 - [c86]Masaru Oya, Masao Yanagisawa, Nozomu Togawa:
Redesign for untrusted gate-level netlists. IOLTS 2016: 219-220 - [c85]Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa:
Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. ISCAS 2016: 978-981 - [c84]Kenta Shimazaki, Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki, Toshitaka Tsuda, Nozomu Togawa:
Hash-table and balanced-tree based FIB architecture for CCN routers. ISOCC 2016: 67-68 - [c83]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A high-performance circuit design algorithm using data dependent approximation. ISOCC 2016: 95-96 - [c82]Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A delay variation and floorplan aware high-level synthesis algorithm with body biasing. ISQED 2016: 75-80 - [c81]Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
In-situ Trojan authentication for invalidating hardware-Trojan functions. ISQED 2016: 152-157 - [c80]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa:
Rotator-based multiplexer network synthesis for field-data extractors. SoCC 2016: 194-199 - 2015
- [j66]Kotaro Terada, Masao Yanagisawa, Nozomu Togawa:
A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1366-1375 (2015) - [j65]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1376-1391 (2015) - [j64]Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1392-1405 (2015) - [j63]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1406-1418 (2015) - [j62]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2484-2493 (2015) - [j61]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2494-2504 (2015) - [j60]Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa:
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2537-2546 (2015) - [j59]Huiqian Jiang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2547-2555 (2015) - [j58]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. Inf. Media Technol. 10(1): 1-7 (2015) - [c79]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
Clock skew estimate modeling for FPGA high-level synthesis and its application. ASICON 2015: 1-4 - [c78]Keita Igarashi, Masao Yanagisawa, Nozomu Togawa:
Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation. ASICON 2015: 1-4 - [c77]Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa:
Small-sized and noise-reducing power analyzer design for low-power IoT devices. ASICON 2015: 1-4 - [c76]Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
A low-power soft error tolerant latch scheme. ASICON 2015: 1-4 - [c75]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. ASICON 2015: 1-4 - [c74]Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa:
A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC 2015: 496-501 - [c73]Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A score-based classification method for identifying hardware-trojans at gate-level netlists. DATE 2015: 465-470 - [c72]Kengo Takeda, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa:
A visible corner-landmark based route finding algorithm for pedestrian navigation. GCCE 2015: 601-602 - [c71]Siya Bao, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa:
A landmark-based route recommendation method for pedestrian walking strategies. GCCE 2015: 672-673 - [c70]Kou Kikuta, Eiji Oki, Naoaki Yamanaka, Nozomu Togawa, Hidenori Nakazato:
Effective Parallel Algorithm for GPGPU-Accelerated Explicit Routing Optimization. GLOBECOM 2015: 1-6 - [c69]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. ICCAD 2015: 682-689 - [c68]Kotaro Terada, Masao Yanagisawa, Nozomu Togawa:
A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. ISCAS 2015: 2129-2132 - [c67]Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. SoCC 2015: 7-12 - [c66]Koki Ito, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa:
Partitioning-based multiplexer network synthesis for field-data extractors. SoCC 2015: 263-268 - 2014
- [j57]Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(7): 1444-1451 (2014) - [j56]Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2434-2442 (2014) - [j55]Yuta Hagio, Masao Yanagisawa, Nozomu Togawa:
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. Inf. Media Technol. 9(4): 446-455 (2014) - [j54]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. IPSJ Trans. Syst. LSI Des. Methodol. 7: 74-80 (2014) - [j53]Yuta Hagio, Masao Yanagisawa, Nozomu Togawa:
A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 7: 81-90 (2014) - [c65]Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. APCCAS 2014: 244-247 - [c64]Kotaro Terada, Masao Yanagisawa, Nozomu Togawa:
A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration. APCCAS 2014: 248-251 - [c63]Huiqian Hang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-based side-channel attack on Camellia cipher using scan signatures. APCCAS 2014: 252-255 - [c62]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. APCCAS 2014: 300-303 - [c61]Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A write-reducing and error-correcting code generation method for non-volatile memories. APCCAS 2014: 304-307 - [c60]Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Secure scan design using improved random order and its evaluations. APCCAS 2014: 555-558 - [c59]Youhua Shi, Nozomu Togawa:
In-situ timing monitoring methods for variation-resilient designs. APCCAS 2014: 735-738 - [c58]Masashi Shio, Masao Yanagisawa, Nozomu Togawa:
Linear and bi-linear interpolation circuits using selector logics and their evaluations. ISCAS 2014: 1436-1439 - [c57]Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-based attack on the LED block cipher using scan signatures. ISCAS 2014: 1460-1463 - [c56]Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Throughput driven check point selection in suspicious timing error prediction based designs. LASCAS 2014: 1-4 - 2013
- [j52]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(1): 312-321 (2013) - [j51]Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(6): 1283-1292 (2013) - [j50]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2597-2611 (2013) - [j49]Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. Inf. Media Technol. 8(3): 867-874 (2013) - [j48]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. Inf. Media Technol. 8(4): 913-923 (2013) - [j47]Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling. IPSJ Trans. Syst. LSI Des. Methodol. 6: 101-111 (2013) - [j46]Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures. J. Inf. Process. 21(3): 572-579 (2013) - [c55]Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-based attack against Trivium stream cipher independent of scan structure. ASICON 2013: 1-4 - [c54]Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi:
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON 2013: 1-4 - [c53]Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. ISCAS 2013: 1432-1435 - [c52]Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa:
A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. ISCAS 2013: 1736-1739 - [c51]Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa:
Suspicious timing error prediction with in-cycle clock gating. ISQED 2013: 335-340 - [c50]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Secure Scan Design with Dynamically Configurable Connection. PRDC 2013: 256-262 - [c49]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT 2013: 1-4 - 2012
- [j45]Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures. IEICE Electron. Express 9(17): 1414-1422 (2012) - [j44]Seungju Lee, Masao Yanagisawa, Nozomu Togawa:
A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(9): 1538-1549 (2012) - [j43]Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
Scan-Based Attack on AES through Round Registers and Its Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2338-2346 (2012) - [j42]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures. Inf. Media Technol. 7(4): 1319-1330 (2012) - [j41]Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa:
A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution. IPSJ Trans. Syst. LSI Des. Methodol. 5: 96-105 (2012) - [j40]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient High-level Synthesis for HDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 5: 106-117 (2012) - [j39]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 176-181 (2012) - [c48]Seungju Lee, Nozomu Togawa, Yusuke Sekihara, Takashi Aoki, Akira Onozawa:
A hybrid NoC architecture utilizing packet transmission priority control method. APCCAS 2012: 404-407 - [c47]Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa:
Scan-based attack against DES cryptosystems using scan signatures. APCCAS 2012: 599-602 - [c46]Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa:
Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. APCCAS 2012: 603-606 - [c45]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. APCCAS 2012: 607-610 - [c44]Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa:
An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures. ISCAS 2012: 576-579 - [c43]Seungju Lee, Nozomu Togawa, Takashi Aoki, Akira Onozawa:
A novel BMNoC configuration algorithm utilizing communication volume and locality among cores. ISCAS 2012: 1668-1671 - [c42]Hiroyuki Akasaka, Masao Yanagisawa, Nozomu Togawa:
Energy-efficient high-level synthesis for HDR architectures with clock gating. ISOCC 2012: 135-138 - [c41]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Dynamically changeable secure scan architecture against scan-based side channel attack. ISOCC 2012: 155-158 - 2011
- [j38]Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Speeding-up exact and fast FIFO-based cache configuration simulation. IEICE Electron. Express 8(14): 1161-1167 (2011) - [j37]Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto:
Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(4): 1082-1090 (2011) - [j36]Mikiko Sode Tanaka, Nozomu Togawa, Masao Yanagisawa, Satoshi Goto:
Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2482-2489 (2011) - [j35]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. Inf. Media Technol. 6(2): 276-285 (2011) - [j34]Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. 6(4): 1076-1091 (2011) - [j33]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scan Vulnerability in Elliptic Curve Cryptosystems. IPSJ Trans. Syst. LSI Des. Methodol. 4: 47-59 (2011) - [j32]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit. IPSJ Trans. Syst. LSI Des. Methodol. 4: 60-69 (2011) - [j31]Sho Tanaka, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 4: 150-165 (2011) - [j30]Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 4: 166-181 (2011) - 2010
- [j29]Ryuta Nara, Kei Satoh, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2481-2489 (2010) - [j28]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1294-1299 (2010) - [c40]Seungju Lee, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers. APCCAS 2010: 712-715 - [c39]Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit. APCCAS 2010: 1083-1086 - [c38]Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS 2010: 1139-1142 - [c37]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scan-based attack against elliptic curve cryptosystems. ASP-DAC 2010: 407-412 - [c36]Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS 2010: 921-924 - [c35]Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS 2010: 1867-1870
2000 – 2009
- 2009
- [j27]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An L1 Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1442-1453 (2009) - [j26]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2304-2317 (2009) - [j25]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3119-3127 (2009) - [j24]Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3169-3179 (2009) - [j23]Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Scan-Based Attack Based on Discriminators for AES Cryptosystems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3229-3237 (2009) - [j22]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Two-Level Cache Design Space Exploration System for Embedded Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3238-3247 (2009) - [c34]Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Exact and fast L1 cache simulation for embedded systems. ASP-DAC 2009: 817-822 - [c33]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Design-for-secure-test for crypto cores. ITC 2009: 1 - 2008
- [j21]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. 91-D(3): 776-780 (2008) - [j20]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1054-1061 (2008) - [j19]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3514-3523 (2008) - [j18]Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. Inf. Media Technol. 3(4): 691-703 (2008) - [j17]Akira Ohchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 1: 78-90 (2008) - [c32]Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Makoto Satoh:
FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm. APCCAS 2008: 701-704 - [c31]Akiyuki Nagashima, Yuta Imai, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. APCCAS 2008: 705-708 - [c30]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unknown response masking with minimized observable response loss and mask data. APCCAS 2008: 1779-1781 - [c29]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
GECOM: Test data compression combined with all unknown response masking. ASP-DAC 2008: 577-582 - [c28]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702 - 2007
- [c27]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS 2007: 149-152 - [c26]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Power-efficient LDPC code decoder architecture. ISLPED 2007: 359-362 - 2006
- [j16]Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier. IEICE Trans. Electron. 89-C(3): 243-249 (2006) - [j15]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 969-978 (2006) - [j14]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 996-1004 (2006) - [j13]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3602-3612 (2006) - [c25]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Memory-Efficient Accelerating Schedule for LDPC Decoder. APCCAS 2006: 1317-1320 - [c24]Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An interface-circuit synthesis method with configurable processor core in IP-based SoC designs. ASP-DAC 2006: 594-599 - [c23]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658 - [c22]Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
A parallel LSI architecture for LDPC decoder improving message-passing schedule. ISCAS 2006 - 2005
- [j12]Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 876-884 (2005) - [j11]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Trans. Inf. Syst. 88-D(7): 1340-1349 (2005) - [j10]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving. IEICE Trans. Inf. Syst. 88-D(7): 1526-1537 (2005) - [c21]Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A processor core synthesis system in IP-based SoC design. ASP-DAC 2005: 286-291 - [c20]Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Reconfigurable adaptive FEC system with interleaving. ASP-DAC 2005: 1252-1255 - [c19]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura:
Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389 - [c18]Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa:
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. ICCD 2005: 503-510 - [c17]Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. ISCAS (4) 2005: 3499-3502 - 2004
- [c16]Jumpei Uchida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A thread partitioning algorithm in low power high-level synthesis. ASP-DAC 2004: 74-79 - [c15]Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A cosynthesis algorithm for application specific processors with heterogeneous datapaths. ASP-DAC 2004: 250-255 - [c14]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC 2004: 743-750 - [c13]Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437 - 2003
- [j9]Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(5): 1082-1092 (2003) - [j8]Nozomu Togawa, Kyosuke Kasahara, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3099-3109 (2003) - [j7]Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3218-3224 (2003) - [c12]Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC 2003: 135-140 - 2002
- [j6]Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 827-834 (2002) - [j5]Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2603-2611 (2002) - [j4]Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A High-Level Energy-Optimizing Algorithm for System VLSIs Based on Area/Time/Power Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2655-2666 (2002) - [c11]Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions. APCCAS (1) 2002: 171-176 - [c10]Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
VLSI Architecture for a Flexible Motion Estimation with Parameters. ASP-DAC/VLSI Design 2002: 452-457 - 2001
- [c9]Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Area/delay estimation for digital signal processor cores. ASP-DAC 2001: 156-161 - 2000
- [c8]Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki:
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). ASP-DAC 2000: 309-312
1990 – 1999
- 1999
- [j3]Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization. J. Circuits Syst. Comput. 9(1-2): 09-112 (1999) - [c7]Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. ASP-DAC 1999: 335-338 - 1998
- [j2]Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 803-818 (1998) - [c6]Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki:
A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs. ASP-DAC 1998: 265-274 - [c5]Nozomu Togawa, Kayoko Hagi, Masao Yanagisawa, Tatsuo Ohtsuki:
An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays. ASP-DAC 1998: 519-526 - 1997
- [j1]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A Performance-Oriented Circuit Partitioning Algorithm with Logic-Block Replication for Multi-FPGA Systems. J. Circuits Syst. Comput. 7(5): 373-394 (1997) - [c4]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. ASP-DAC 1997: 569-578 - 1995
- [c3]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization. ASP-DAC 1995 - 1994
- [c2]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays. ICCAD 1994: 156-163 - [c1]Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A Simultaneous Placement and Global Routing Algorithm for FPGAs. ISCAS 1994: 483-486
Coauthor Index
[j39] [j35] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [c40] [c39] [c38] [c37] [c36] [c35] [j27] [j26] [j25] [j24] [j23] [j22] [c34] [c33] [j21] [j19] [j18] [j17] [c32] [c31] [c30] [c29] [c28] [c27] [j16] [j14] [c24] [c23] [j12] [j11] [c21] [c19] [c17] [c16] [c15] [c14] [c13] [j9] [j8] [j7] [c12] [j6] [j5] [j4] [c11] [c10] [c9] [c8] [j3] [c7] [j2] [c6] [c5] [j1] [c4] [c3] [c2] [c1]
[j98] [j97] [c136] [j96] [j95] [j94] [j91] [c133] [c127] [c126] [c123] [c122] [j90] [j89] [j88] [j87] [j86] [j85] [j84] [j83] [c119] [c118] [c117] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [c109] [c108] [c106] [j81] [j80] [j79] [j78] [j77] [j76] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [j74] [j73] [j72] [j71] [j70] [j69] [j68] [c91] [c90] [c89] [c88] [c87] [c86] [c85] [c83] [c82] [c81] [c80] [j66] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [j58] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [c71] [c69] [c68] [c67] [c66] [j57] [j56] [j55] [j54] [j53] [c65] [c64] [c63] [c62] [c61] [c60] [c58] [c57] [c56] [j52] [j51] [j50] [j49] [j48] [j47] [j46] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [c47] [c46] [c45] [c44] [c42] [c41] [j38] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [j30] [j29] [j28] [c40] [c39] [c38] [c37] [c36] [c35] [j27] [j26] [j25] [j24] [j23] [j22] [c34] [c33] [j21] [j19] [j18] [j17] [c32] [c31] [c30] [c29] [c28] [c27] [j16] [j14] [c24] [c23] [j12] [j11] [c21] [c19] [c17] [c16] [c15] [c14] [c13] [j9] [j8] [j7] [c12] [j6] [j5] [j4] [c11] [c10] [c9] [c8] [j3] [c7] [j2] [c6] [c5]
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