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ORCIDChris R. Jesshope
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2010 – 2019
- 2014
[j34]Muhammad Irfan Uddin
, Raphael Poss, Chris R. Jesshope:
Cache-based high-level simulation of microthreaded many-core architectures. J. Syst. Archit. 60(7): 529-552 (2014)- [j33]Qiang Yang, Jian Fu, Raphael Poss, Chris R. Jesshope:
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches. ACM Trans. Embed. Comput. Syst. 13(3s): 103:1-103:21 (2014) - [c56]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors. ARES 2014: 88-93 - [c55]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
A fault detection mechanism in a Data-flow scheduled Multithreaded processor. DATE 2014: 1-4 - [c54]Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope:
Analytical-Based High-Level Simulation of the Microthreaded Many-Core Architectures. PDP 2014: 344-351 - [c53]Muhammad Irfan Uddin, Raphael Poss, Chris R. Jesshope:
Signature-based high-level simulation of microthreaded many-core architectures. SIMULTECH 2014: 509-516 - 2013
- [j32]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Muhammad Irfan Uddin, Chris R. Jesshope:
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. Microprocess. Microsystems 37(8-C): 1090-1101 (2013) - [c52]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - A simulation environment for multi-core research and education. ICSAMOS 2013: 80-87 - [c51]Jian Fu, Qiang Yang, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang:
On-demand thread-level fault detection in a concurrent programming environment. ICSAMOS 2013: 255-262 - [i1]Mike Lankamp, Raphael 'kena' Poss, Qiang Yang, Jian Fu, Muhammad Irfan Uddin, Chris R. Jesshope:
MGSim - Simulation tools for multi-core processor architectures. CoRR abs/1302.1390 (2013) - 2012
- [c50]Raphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, Michiel W. van Tol, Chris R. Jesshope:
Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. DSD 2012: 501-508 - [c49]Muhammad Irfan Uddin, Chris R. Jesshope, Michiel W. van Tol, Raphael Poss:
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores. RAPIDO 2012: 1-8 - 2011
- [j31]Muhammad Irfan Uddin, Michiel W. van Tol, Chris R. Jesshope:
High Level Simulation of SVP Many-Core Systems. Parallel Process. Lett. 21(4): 413-438 (2011) - [c48]Qiang Yang, Chris R. Jesshope, Jian Fu:
A Micro Threading Based Concurrency Model for Parallel Computing. IPDPS Workshops 2011: 1668-1674 - [c47]Michiel W. van Tol, Roy Bakker, Merijn Verstraaten, Clemens Grelck, Chris R. Jesshope:
Efficient Memory Copy Operations on the 48-core Intel SCC Processor. MARC Symposium 2011: 13-18 - [c46]Merijn Verstraaten, Clemens Grelck, Michiel W. van Tol, Roy Bakker, Chris R. Jesshope:
Mapping Distributed S-Net on the 48-core Intel SCC processor. MARC Symposium 2011: 41-46 - [c45]Clemens Grelck, Kevin Hammond, Heinz Hertlein, Philip K. F. Hölzenspies, Chris R. Jesshope, Raimund Kirner, Bernd Scheuermann, Alexander V. Shafarenko, Iraneus te Boekhorst, Volkmar Wieser:
Engineering Concurrent Software Guided by Statistical Performance Analysis. PARCO 2011: 385-394 - 2010
- [j30]Thomas A. M. Bernard, Clemens Grelck, Chris R. Jesshope:
On the Compilation of a Language for General Concurrent Target Architectures. Parallel Process. Lett. 20(1): 51-69 (2010) - [c44]Thomas A. M. Bernard, Clemens Grelck, Michael A. Hicks, Chris R. Jesshope, Raphael Poss:
Resource-Agnostic Programming for Many-Core Microgrids. Euro-Par Workshops 2010: 109-116 - [c43]Michiel W. van Tol, Chris R. Jesshope:
An Operating System Strategy for General-purpose Parallel Computing on Many-core Architectures. High Performance Computing Workshop 2010: 157-181 - [c42]Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope:
Towards scalable I/O on a many-core architecture. ICSAMOS 2010: 341-348
2000 – 2009
- 2009
- [j29]Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp:
Implementation and evaluation of a microthread architecture. J. Syst. Archit. 55(3): 149-161 (2009) - [j28]Michiel W. van Tol, Chris R. Jesshope, Mike Lankamp, Simon Polstra:
An implementation of the SANE Virtual Processor using POSIX threads. J. Syst. Archit. 55(3): 162-169 (2009) - [j27]Chris R. Jesshope, Mike Lankamp, Li Zhang:
The implementation of an SVP many-core processor and the evaluation of its memory architecture. SIGARCH Comput. Archit. News 37(2): 38-45 (2009) - [c41]Chris R. Jesshope, Mike Lankamp, Li Zhang:
Evaluating CMPs and Their Memory Architecture. ARCS 2009: 246-257 - [c40]Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff:
HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops 2009: 9-15 - [c39]Chris R. Jesshope, Michael A. Hicks, Mike Lankamp, Raphael 'kena' Poss, Li Zhang:
Making multi-cores mainstream - from security to scalability. PARCO 2009: 16-31 - 2008
- [j26]Chris R. Jesshope:
Operating Systems in silicon and the Dynamic Management of Resources in Many-Core Chips. Parallel Process. Lett. 18(2): 257-274 (2008) - [c38]Chris R. Jesshope, Alexander V. Shafarenko:
Concurrency engineering. ACSAC 2008: 1-8 - [c37]Thuy Duong Vu, Li Zhang, Chris R. Jesshope:
The Verification of the On-Chip COMA Cache Coherence Protocol. AMAST 2008: 413-429 - [c36]Chris R. Jesshope:
Building a Concurrency and Resource Allocation Model into a Processor's ISA. Euro-Par Workshops 2008: 129-130 - [c35]Thomas A. M. Bernard, Kostas Bousias, Liang Guang, Chris R. Jesshope, Mike Lankamp, Michiel W. van Tol, Li Zhang:
A general model of concurrency and its implementation as many-core dynamic RISC processors. ICSAMOS 2008: 1-9 - [c34]Chris R. Jesshope:
Introduction to Programming Multicores. SAMOS 2008: 207 - [c33]Chris R. Jesshope, Jean-Marc Philippe, Michiel W. van Tol:
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency. SAMOS 2008: 218-228 - 2007
- [j25]Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope:
Asynchronous arbiter for micro-threaded chip multiprocessors. J. Syst. Archit. 53(5-6): 253-262 (2007) - [c32]Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope:
High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids. AICCSA 2007: 301-308 - [c31]Li Zhang, Chris R. Jesshope:
On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores. Euro-Par Workshops 2007: 38-48 - [c30]Thuy Duong Vu, Chris R. Jesshope:
Formalizing SANE Virtual Processor in Thread Algebra. ICFEM 2007: 345-365 - [c29]Thomas A. M. Bernard, Chris R. Jesshope, Peter M. W. Knijnenburg:
Strategies for Compiling µ TC to Novel Chip Multiprocessors. SAMOS 2007: 127-138 - [e4]Keqiu Li, Chris R. Jesshope, Hai Jin, Jean-Luc Gaudiot:
Network and Parallel Computing, IFIP International Conference, NPC 2007, Dalian, China, September 18-21, 2007, Proceedings. Lecture Notes in Computer Science 4672, Springer 2007, ISBN 978-3-540-74783-3 [contents] - 2006
- [j24]Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope:
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors. Comput. J. 49(2): 211-233 (2006) - [j23]Chris R. Jesshope, Alexander V. Shafarenko:
Special issue on Micro-grids - Guest Editor Introduction. Int. J. Parallel Program. 34(3): 189-192 (2006) - [j22]Chris R. Jesshope, Alexander V. Shafarenko:
Guest Editor's Introduction (Part 2). Int. J. Parallel Program. 34(4): 319-322 (2006) - [j21]Ian M. Bell, Nabil Hasasneh, Chris R. Jesshope:
Supporting Microthread Scheduling and Synchronisation in CMPs. Int. J. Parallel Program. 34(4): 343-381 (2006) - [j20]Chris R. Jesshope:
Microthreading a Model for Distributed Instruction-level Concurrency. Parallel Process. Lett. 16(2): 209-228 (2006) - [c28]Chris R. Jesshope:
muTC - An Intermediate Language for Programming Chip Multiprocessors. Asia-Pacific Computer Systems Architecture Conference 2006: 147-160 - [c27]Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope:
Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors. ARCS 2006: 252-267 - [c26]Chris R. Jesshope:
A Model for the Design and Programming of Multi-cores. High Performance Computing Workshop 2006: 37-55 - [e3]Chris R. Jesshope, Colin Egan:
Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings. Lecture Notes in Computer Science 4186, Springer 2006, ISBN 3-540-40056-7 [contents] - 2005
- [c25]Kostas Bousias, Chris R. Jesshope:
The Challenges of Massive On-Chip Concurrency. Asia-Pacific Computer Systems Architecture Conference 2005: 157-170 - 2004
- [c24]Chris R. Jesshope:
Microgrids - The exploitation of massive on-chip concurrency. High Performance Computing Workshop 2004: 203-223 - [c23]Lipeng Wen, Chris R. Jesshope:
A General Learning Management System Based on Schema-driven Methodology. ICALT 2004 - [c22]Chris R. Jesshope:
Scalable Instruction-Level Parallelism.. SAMOS 2004: 383-392 - 2003
- [c21]Chris R. Jesshope:
Multi-threaded Microprocessors - Evolution or Revolution. Asia-Pacific Computer Systems Architecture Conference 2003: 21-45 - [c20]Lipeng Wen, Chris R. Jesshope:
Web Services Technology and Learning Technology- A Web-Services Model for Constructing Decentralized Virtual Learning Environments. ICWS 2003: 507-514 - 2001
- [j19]Chris R. Jesshope:
Cost-Effective Multimedia in On-line Teaching. J. Educ. Technol. Soc. 4(3) (2001) - [c19]Chris R. Jesshope:
Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. ACSAC 2001: 80-88 - [c18]Ramón Beivide, Chris R. Jesshope, Antonio Robles, Cruz Izu:
Topic 12: Routing and Communication in Interconnection Networks. Euro-Par 2001: 611-612 - [c17]Regina Gehne, Chris R. Jesshope, Zhenzi Zhang:
Technology Integrated Learning Environment - A Web-based Distance Learning System. IMSA 2001: 1-6 - [c16]Hong Hong, Neena Albi, Kinshuk, Xiaoqin He, Ashok Patel, Chris R. Jesshope:
Adaptivity in Web-based Educational System. WWW Posters 2001 - 2000
- [c15]Chris R. Jesshope, Bing Luo:
Micro-Threading: A New Approach to Future RISC. ACAC 2000: 34-41
1990 – 1999
- 1999
- [j18]Chris R. Jesshope:
Computers as Tutors: Solving the Crisis in Education. J. Educ. Technol. Soc. 2(4) (1999) - [c14]Chris R. Jesshope:
Parallel Computer Architecture - What Is Its Future? Introduction. Euro-Par 1999: 695-697 - 1998
- [c13]Murray Pearson, Chris R. Jesshope:
Multi-campus teaching using computer networks. ACSE 1998: 106-111 - 1997
- [j17]Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope:
Optical Interconnectivity in a Scalable Data-Parallel System. J. Parallel Distributed Comput. 41(1): 120-130 (1997) - [c12]Chris R. Jesshope:
Web based teaching: a minimalist approach. ACSE 1997: 16-23 - 1996
- [c11]Julian A. B. Dines, John F. Snowdon, Marc P. Y. Desmulliez, D. T. Nielson, Dima B. Barsky, Alexander V. Shafarenko, Chris R. Jesshope:
Optical Interconnection hardware for scalable systems. PDPTA 1996: 367-374 - [c10]Horia C. Slusanschi, Chris R. Jesshope:
A FORTRAN 90 to F-code Compiler. UK Parallel 1996: 40-52 - [e2]Chris R. Jesshope, Shasha Shafarenko:
UK Parallel '96 - Proceedings of the BCS PPSG Annual Conference, Surrey, UK, July 3-5, 1996. BCS Conference Series, Springer 1996, ISBN 978-3-540-76068-9 [contents] - 1995
- [j16]Chris R. Jesshope:
Multiprocessing: Trade-offs in computation and communication : Vijay K Naik Kluwer Academic Publishers, Dordrecht, The Netherlands (1993) ISBN 0 7923 9370 8, Dfl 180.00, £65.50, pp224. Microprocess. Microsystems 19(2): 107 (1995) - [c9]I. Ashman, T. Vladimirova, Chris R. Jesshope, R. Peel:
Parallel Boltzmann Machine Topologies for Simulated Annealing Realisation of Combinatorial Problems. ICANNGA 1995: 297-300 - 1994
- [j15]Chris R. Jesshope:
Mechanized Reasoning and Hardware Design: C A R Hoare and M J C Gordon (Eds) Prentice Hall, Hemel Hempstead, UK (1992) ISBN 0 13 572405 8, £40, pp 151. Microprocess. Microsystems 18(1): 53 (1994) - [c8]Chris R. Jesshope, Ivailo M. Nedelchev:
Asynchronous packet routers. Interconnection Networks and Mapping and Scheduling Parallel Computations 1994: 211-227 - [c7]Ivailo M. Nedelchev, Chris R. Jesshope:
Basic building blocks for asynchronous packet routers. Great Lakes Symposium on VLSI 1994: 184-187 - [c6]Cruz Izu, Ramón Beivide, Chris R. Jesshope:
Mad-postman : A Look-ahead Message Propagation Method For Static Bidimensional Meshes. PDP 1994: 117-124 - [e1]Chris R. Jesshope, Vesselin Jossifov, Wolfgang Wilhelmi:
Parcella 1994, VI. International Workshop on Parallel Processing by Cellular Automata and Arrays, Potsdam, Germany, September 21-23, 1994. Proceedings. Mathematical Research 81, Akademie Verlag, Berlin 1994, ISBN 3-05-501602-5 [contents] - 1993
- [j14]Chris R. Jesshope, Cruz Izu:
The MP1 Network Chip and its Application to Parallel Computers. Comput. J. 36(8): 763-777 (1993) - [j13]Cruz Izu, Ramón Beivide, Chris R. Jesshope, Agustin Arruabarrena:
Experimental evaluation of Mad Postman bidimensional routing networks. Microprocess. Microprogramming 38(1-5): 33-41 (1993) - [j12]Chris R. Jesshope:
Latency Reduction in VLSI Routers. Parallel Process. Lett. 3: 485-494 (1993) - [c5]Chris R. Jesshope, Cruz Izu:
The MP1 network chip. PDP 1993: 338-348 - 1991
- [j11]Chris R. Jesshope:
Computing with parallel architectures: T.node: Gassilloud, D and Grossetie, J C (Eds) Kluwer (1991) pp 241, £52, ISBN 0792-31225-2. Microprocess. Microsystems 15(7): 395-396 (1991) - [c4]Vladimir Getov, Chris R. Jesshope:
Simulation Facility of Distributed Memory System with "Mad Postman" Communication Network. EDMCC 1991: 224-233 - 1990
- [j10]Chris R. Jesshope:
Distributed computer systems: Zedan, H S M (Ed.) Butterworths, Borough Green, UK (1990) £48.00, pp 313. Microprocess. Microsystems 14(7): 483-484 (1990)
1980 – 1989
- 1989
- [j9]Chris R. Jesshope:
Parallel processing, the transputer and the future. Microprocess. Microsystems 13(1): 33-37 (1989) - [j8]Chris R. Jesshope:
Editorial. Microprocess. Microsystems 13(2): 66 (1989) - [j7]Chris R. Jesshope:
Editorial. Microprocess. Microsystems 13(3): 147 (1989) - [j6]Chris R. Jesshope:
Parallel program design: a foundation: Chandry, K M and Misra, J Addison-Wesley, Wokingham, UK (1988) £19.95 pp 516. Microprocess. Microsystems 13(7): 484 (1989) - [c3]Chris R. Jesshope, P. R. Miller, Jay T. Yantchev:
High Performance Communications in Processor Networks. ISCA 1989: 150-157 - 1988
- [j5]Chris R. Jesshope:
MUNAP: an unusual computer with clear implications: Baba, TMicroprogrammable parallel computers MIT Press, Cambridge, MA, USA (1987) £26.95 pp 290. Microprocess. Microsystems 12(2): 118 (1988) - [j4]Chris R. Jesshope:
Transputers and switches as objects in OCCAM. Parallel Comput. 8(1-3): 19-30 (1988) - [c2]Chris R. Jesshope:
Reconfigurable transputer systems. C³P 1988: 105-114 - [c1]Chris R. Jesshope, Philip Miller, Jelio Yantchev:
Programming with active data. Parcella 1988: 111-129 - 1985
- [j3]Chris R. Jesshope, M. J. Crawley, G. L. Lovegrove:
An Intelligent Pascal Editor for a Graphical Oriented Workstation. Softw. Pract. Exp. 15(11): 1103-1119 (1985) - 1980
- [j2]Chris R. Jesshope:
The Implementation of Fast Radix 2 Transforms on Array Processors. IEEE Trans. Computers 29(1): 20-27 (1980) - [j1]Chris R. Jesshope:
Some Results Concerning Data Routing in Array Processors. IEEE Trans. Computers 29(7): 659-662 (1980)
Coauthor Index
Raphael 'kena' Poss
aka: Raphael Poss
aka: Raphael Poss
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