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ORCIDSachin Maheshwari
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2020 – today
- 2023
[c12]Sachin Maheshwari, Jiaqi Wang, Alexander Serb, Themistoklis Prodromakis:
A Memristor-based Tuneable Offset Comparator. NEWCAS 2023: 1-5- 2022
- [j10]Sachin Maheshwari
, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis:
An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9): 3512-3525 (2022) - [c11]Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G. Constandinou:
A CMOS-based Characterisation Platform for Emerging RRAM Technologies. ISCAS 2022: 75-79 - [i4]Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis:
An Adiabatic Capacitive Artificial Neuron with RRAM-based Threshold Detection for Energy-Efficient Neuromorphic Computing. CoRR abs/2202.01144 (2022) - [i3]Andrea Mifsud, Jiawei Shen, Peilong Feng, Lijie Xie, Chaohan Wang, Yihan Pan, Sachin Maheshwari, Shady Agwa, Spyros Stathopoulos, Shiwei Wang, Alexander Serb, Christos Papavassiliou, Themis Prodromakis, Timothy G. Constandinou:
A CMOS-based Characterisation Platform for Emerging RRAM Technologies. CoRR abs/2205.08379 (2022) - 2021
- [j9]Jiaqi Wang, Alexantrou Serb, Christos Papavassiliou, Sachin Maheshwari, Themis Prodromakis:
Analysing and measuring the performance of memristive integrating amplifiers. Int. J. Circuit Theory Appl. 49(11): 3507-3525 (2021) - [j8]Sachin Maheshwari, Viv A. Bartlett, Izzet Kale:
A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1721-1725 (2021) - [j7]Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis:
Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 4862-4875 (2021) - [j6]Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis:
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 4876-4888 (2021) - [c10]Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis:
An Adiabatic Regenerative Capacitive Artificial Neuron. ISCAS 2021: 1-5 - 2020
- [j5]Brijpal Singh, Zahid A. Khan, Arshad Noor Siddiquee, Sachin Maheshwari:
Optimal design of flux for submerged arc weld properties based on RSM coupled with GRA and PCA. Int. J. Manuf. Technol. Manag. 34(1): 97-109 (2020) - [i2]Jiaqi Wang, Alexander Serb, Christos Papavassiliou, Sachin Maheshwari, Themistoklis Prodromakis:
Analysing and Measuring the Performance ofMemristive Integrating Amplifiers. CoRR abs/2009.09909 (2020) - [i1]Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Lieuwe B. Leene, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis:
Hybrid CMOS/Memristor Circuit Design Methodology. CoRR abs/2012.02267 (2020)
2010 – 2019
- 2019
- [j4]Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach. Integr. 67: 144-154 (2019) - [c9]Sachin Maheshwari, Izzet Kale:
Adiabatic Implementation of Manchester Encoding for Passive NFC System. DATE 2019: 1615-1618 - [c8]Sachin Maheshwari, Izzet Kale:
Impact of Adiabatic Logic Families on the Power-Clock Generator Energy Efficiency. PRIME 2019: 25-28 - 2018
- [j3]Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication. Integr. 62: 341-352 (2018) - [c7]Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design. PATMOS 2018: 111-117 - 2017
- [c6]Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale:
Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers. ECCTD 2017: 1-4 - 2014
- [c5]Sachin Maheshwari, Jimit Patel, Sumit K. Nirmalkar, Anu Gupta:
Logical effort based power-delay-product optimization. ICACCI 2014: 565-569 - 2013
- [c4]Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh:
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology. VDAT 2013: 100-107 - [c3]Sachin Maheshwari, Himadri Singh Raghav, Anu Gupta:
Characterization of Logical Effort for Improved Delay. VDAT 2013: 108-117 - [c2]Sachin Maheshwari, Rameez Raza, Pramod Kumar, Anu Gupta:
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology. VDAT 2013: 185-193 - 2011
- [c1]Pushpendrai Singh Bharti, Sachin Maheshwari, Chitra Sharma:
Neural-Network- Based Modeling of Electric Discharge Machining Process. SOCO 2011: 95-103 - 2010
- [j2]Shankar Singh, Sachin Maheshwari, Aloke Dey, Poorn Chandra Pandey:
Experimental results and analysis for Electrical Discharge Machining (EDM) of aluminium metal matrix composites with powder-mixed dielectric: Lenth's method. Int. J. Manuf. Technol. Manag. 21(1/2): 67-82 (2010)
2000 – 2009
- 2007
- [j1]Shankar Singh, Sachin Maheshwari, Poorn Chandra Pandey:
Optimisation of multiperformance characteristics in electric discharge machining of Aluminium Matrix Composites (AMCs) using Taguchi DOE methodology. Int. J. Manuf. Res. 2(2): 138-161 (2007)
Coauthor Index
aka: Themis Prodromakis
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