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ORCIDPaul D. Franzon
Paul Franzon
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- affiliation: North Carolina State University, Raleigh, USA
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2020 – today
- 2024
[j42]Archit Gajjar
, Priyank Kashyap, Aydin Aysu, Paul Franzon, Yongjin Choi, Chris Cheng, Giacomo Pedretti, Jim Ignowski:
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost. ACM Trans. Reconfigurable Technol. Syst. 17(4): 56:1-56:33 (2024)- [c101]Eren Kurshan, Paul D. Franzon:
Towards 3D AI Hardware: Fine-Grain Hardware Characterization of 3D Stacks for Heterogeneous System Integration & AI Systems. 3DIC 2024: 1-6 - [c100]Ahmad Bennakhi, Gregory T. Byrd, Paul Franzon:
Solving the B-SAT Problem Using Quantum Computing: Smaller is Sometimes Better. Allerton 2024: 1-8 - [c99]Ahmad Bennakhi, Gregory T. Byrd, Paul Franzon:
Analyzing Quantum Circuit Depth Reduction with Ancilla Qubits in MCX Gates. QCE 2024: 510-511 - [i5]Fin Amin, Nirjhor Rouf, Tse-Han Pan, Md Kamal Ibn Shafi, Paul D. Franzon:
Large Reasoning Models for 3D Floorplanning in EDA: Learning from Imperfections. CoRR abs/2406.10538 (2024) - [i4]Nirjhor Rouf, Fin Amin, Paul D. Franzon:
Can Low-Rank Knowledge Distillation in LLMs be Useful for Microelectronic Reasoning? CoRR abs/2406.13808 (2024) - [i3]Ahmad Bennakhi, Paul Franzon, Gregory T. Byrd:
Analyzing Quantum Circuit Depth Reduction with Ancilla Qubits in MCX Gates. CoRR abs/2408.01304 (2024) - [i2]Eren Kurshan, Paul Franzon:
Towards 3D AI Hardware: Fine-Grain Hardware Characterization of 3D Stacks for Heterogeneous System Integration & AI Systems. CoRR abs/2409.10539 (2024) - 2023
- [j41]Luis Francisco, W. Rhett Davis, Paul D. Franzon:
A Deep Transfer Learning Design Rule Checker With Synthetic Training. IEEE Des. Test 40(1): 77-84 (2023) - [c98]Priyank Kashyap, Prasanth Prabu Ravichandiran, Lee Wang, Dror Baron, Chau-Wai Wong, Tianfu Wu, Paul D. Franzon:
Thermal Estimation for 3D-ICs Through Generative Networks. 3DIC 2023: 1-4 - [c97]Joshua A. Stevens, Tse-Han Pan, Prasanth Prabu Ravichandiran, Paul D. Franzon:
Chiplet Set For Artificial Intelligence. 3DIC 2023: 1-5 - [c96]Pouria Zaghari, Sourish S. Sinha, Jong Eun Ryu, Paul D. Franzon, Douglas C. Hopkins:
Thermal Cycling and Fatigue Life Analysis of a Laterally Conducting GaN-based Power Package. 3DIC 2023: 1-5 - [c95]Fin Amin, Soumyadeep Chatterjee, Paul D. Franzon:
DepthGraphNet: Circuit Graph Isomorphism Detection via Siamese-Graph Neural Networks. MLCAD 2023: 1-6 - 2022
- [j40]Weifu Li, Paul D. Franzon, Sumon Dey, Joshua Schabel:
Hardware Implementation of Hierarchical Temporal Memory Algorithm. ACM J. Emerg. Technol. Comput. Syst. 18(1): 17:1-17:23 (2022) - [j39]Haifeng Wang, Zheng Li, Yong Liu, Xiang Chen, Paul D. Franzon, Yuxiaoyang Cai, Luxi Fan:
Can Higher-Order Mutants Improve the Performance of Mutation-Based Fault Localization? IEEE Trans. Reliab. 71(2): 1157-1173 (2022) - [j38]Theodros Nigussie, Joshua Schabel, Steve Lipa, Lisa G. McIlrath, Robert Patti, Paul D. Franzon:
Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1230-1243 (2022) - [c94]Archit Gajjar, Priyank Kashyap, Aydin Aysu, Paul D. Franzon, Sumon Dey, Chris Cheng:
FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS. FCCM 2022: 1-9 - [c93]Yuejiang Wen, Jacob Dean, Brian A. Floyd, Paul D. Franzon:
High Dimensional Optimization for Electronic Design. MLCAD 2022: 153-157 - [c92]Priyank Kashyap, Archit Gajjar, Yongjin Choi, Chau-Wai Wong, Dror Baron, Tianfu Wu, Chris Cheng, Paul D. Franzon:
RxGAN: Modeling High-Speed Receiver through Generative Adversarial Networks. MLCAD 2022: 167-172 - 2021
- [j37]Sumon Dey, Lee Baker, Joshua Schabel, Weifu Li, Paul D. Franzon:
A Scalable Cluster-based Hierarchical Hardware Accelerator for a Cortically Inspired Algorithm. ACM J. Emerg. Technol. Comput. Syst. 17(4): 52:1-52:29 (2021) - [j36]Priyank Kashyap, Furkan Aydin, Seetal Potluri, Paul D. Franzon, Aydin Aysu:
2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1217-1229 (2021) - [c91]Lee Baker, Robert Patti, Paul D. Franzon:
Multi-ANN embedded system based on a custom 3D-DRAM. 3DIC 2021: 1-7 - [c90]Prasanth Prabu Ravichandiran, Paul D. Franzon:
A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation. 3DIC 2021: 1-6 - [c89]W. Rhett Davis, Paul D. Franzon, Luis Francisco, Billy Huggins, Rajeev Jain:
Fast and Accurate PPA Modeling with Transfer Learning. ICCAD 2021: 1-8 - [c88]Luis Francisco, Paul D. Franzon, W. Rhett Davis:
Fast and Accurate PPA Modeling with Transfer Learning. MLCAD 2021: 1-6 - 2020
- [j35]Yi Wang, Paul D. Franzon, David Smart, Brian Swahn:
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration. ACM Trans. Design Autom. Electr. Syst. 25(5): 45:1-45:21 (2020) - [c87]Francesco Regazzoni, Shivam Bhasin, Amir Alipour, Ihab Alshaer, Furkan Aydin, Aydin Aysu, Vincent Beroulle, Giorgio Di Natale, Paul D. Franzon, David Hély, Naofumi Homma, Akira Ito, Dirmanto Jap, Priyank Kashyap, Ilia Polian, Seetal Potluri, Rei Ueno, Elena-Ioana Vatajelu, Ville Yli-Mäyry:
Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-. ICCAD 2020: 141:1-141:6 - [c86]Luis Francisco, Tanmay Lagare, Arpit Jain, Somal Chaudhary, Madhura Kulkarni, Divya Sardana, W. Rhett Davis, Paul D. Franzon:
Design Rule Checking with a CNN Based Feature Extractor. MLCAD 2020: 9-14 - [c85]Isaac Turtletaub, George Li, Mohannad Ibrahim, Paul D. Franzon:
Application of Quantum Machine Learning to VLSI Placement. MLCAD 2020: 61-66 - [c84]Furkan Aydin, Priyank Kashyap, Seetal Potluri, Paul D. Franzon, Aydin Aysu:
DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks. SAMOS 2020: 262-280 - [i1]Luis Francisco, Tanmay Lagare, Arpit Jain, Somal Chaudhary, Madhura Kulkarni, Divya Sardana, W. Rhett Davis, Paul D. Franzon:
Design Rule Checking with a CNN Based Feature Extractor. CoRR abs/2012.11510 (2020)
2010 – 2019
- 2019
- [j34]Jong Beom Park, William Rhett Davis, Paul D. Franzon:
3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 756-768 (2019) - [j33]Sung-Wook Park, Lee Baker, Paul D. Franzon:
Appliance Identification Algorithm for a Non-Intrusive Home Energy Monitor Using Cogent Confabulation. IEEE Trans. Smart Grid 10(1): 714-721 (2019) - [c83]T. Robert Harris, W. Rhett Davis, Steven Lipa, W. Shepherd Pitts, Paul D. Franzon:
Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages. 3DIC 2019: 1-3 - [c82]Zhao Wang, Aranya Chakrabortty, C. T. Kelley, Xiaoming Feng, Paul D. Franzon:
Improved Numerical Methodologies on Power System Dynamic Simulation Using GPU Implementation. ISGT 2019: 1-5 - [c81]Sumon Dey, Paul D. Franzon:
An Application Specific Processor Architecture with 3D Integration for Recurrent Neural Networks. ISQED 2019: 183-190 - [c80]Billy Huggins, W. Rhett Davis, Paul D. Franzon:
Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools. ISQED 2019: 304-310 - 2018
- [j32]Joshua Schabel, Paul D. Franzon:
Exploring the Tradeoffs of Application-Specific Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 531-542 (2018) - [j31]Wenxu Zhao, Peter Gadfort, Kirti Bhanushali, Paul D. Franzon:
RF-Only Logic: an Area Efficient Logic Family for RF-Power Harvesting Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 406-418 (2018) - 2017
- [j30]HoonSeok Kim, Chanyoun Won, Paul D. Franzon:
Corrections to "Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding". IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1792 (2017) - [c79]Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor. ICCD 2017: 145-152 - [c78]Eric J. Wyers, Weiyi Qi, Paul D. Franzon:
A robust calibration and supervised machine learning reliability framework for digitally-assisted self-healing RFICs. MWSCAS 2017: 1138-1141 - 2016
- [j29]Eric J. Wyers, Matthew A. Morton, T. C. L. Gerhard Sollner, C. T. Kelley, Paul D. Franzon:
A Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing RFICs. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1151-1164 (2016) - [c77]Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
Physical design of a 3D-stacked heterogeneous multi-core processor. 3DIC 2016: 1-5 - [c76]Joshua Schabel, Lee Baker, Sumon Dey, Weifu Li, Paul D. Franzon:
Processor-in-memory support for artificial neural networks. ICRC 2016: 1-8 - [c75]Wenxu Zhao, Kirti Bhanushali, Paul D. Franzon:
Design of a rectifier-free UHF Gen-2 compatible RFID Tag using RF-only logic. IEEE RFID 2016: 93-98 - [c74]Sumon Dey, Paul D. Franzon:
Design and ASIC acceleration of cortical algorithm for text recognition. SoCC 2016: 114-119 - [c73]Weifu Li, Paul D. Franzon:
Hardware implementation of Hierarchical Temporal Memory algorithm. SoCC 2016: 133-138 - 2015
- [c72]T. Robert Harris, Eric J. Wyers, Lee Wang, Samuel Graham, Georges Pavlidis, Paul D. Franzon, W. Rhett Davis:
Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks. 3DIC 2015: TS10.2.1-TS10.2.4 - [c71]Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa:
Computing in 3D. 3DIC 2015: TS6.1.1-TS6.1.2 - [c70]Eric J. Wyers, T. Robert Harris, Wallace Shep Pitts, Jordan E. Massad, Paul D. Franzon:
Characterization of the mechanical stress impact on device electrical performance in the CMOS and III-V HEMT/HBT heterogeneous integration environment. 3DIC 2015: TS8.27.1-TS8.27.4 - [c69]Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Steve Lipa:
Computing in 3D. CICC 2015: 1-6 - [c68]Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. Hot Chips Symposium 2015: 1 - 2014
- [j28]Ojas A. Bapat, Paul D. Franzon, Richard M. Fastow:
A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2701-2712 (2014) - [c67]Paul D. Franzon, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel:
3D-enabled customizable embedded computer (3DECC). 3DIC 2014: 1-3 - [c66]T. Robert Harris, Paul D. Franzon, W. Rhett Davis, Lee Wang:
Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits. 3DIC 2014: 1-3 - [c65]Randy Widialaksono, Wenxu Zhao, W. Rhett Davis, Paul D. Franzon:
Leveraging 3D-IC for on-chip timing uncertainty measurements. 3DIC 2014: 1-4 - [c64]Shivam Priyadarshi, W. Rhett Davis, Paul D. Franzon:
Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC. ICICDT 2014: 1-6 - 2013
- [j27]Eric J. Wyers, Michael B. Steer, C. T. Kelley, Paul D. Franzon:
A Bounded and Discretized Nelder-Mead Algorithm Suitable for RFIC Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(7): 1787-1799 (2013) - [j26]HoonSeok Kim, Chanyoun Won, Paul D. Franzon:
Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1562-1567 (2013) - [c63]Paul D. Franzon, Avi Bar-Cohen:
Thermal requirements in future 3D processors. 3DIC 2013: 1-6 - [c62]Edward J. Suh, Paul D. Franzon:
Design of 60 GHz contactless probe system for RDL in passive silicon interposer. 3DIC 2013: 1-5 - [c61]Nyunyi M. Tshibangu, Paul D. Franzon, Eric Rotenberg, William Rhett Davis:
Design of controller for L2 cache mapped in Tezzaron stacked DRAM. 3DIC 2013: 1-4 - [c60]Zhenqian Zhang, Paul D. Franzon:
TSV-based, modular and collision detectable face-to-back shared bus design. 3DIC 2013: 1-5 - [c59]Zhenqian Zhang, Brandon Noia, Krishnendu Chakrabarty, Paul D. Franzon:
Face-to-face bus design with built-in self-test in 3D ICs. 3DIC 2013: 1-7 - [c58]Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon:
Rationale for a 3D heterogeneous multi-core processor. ICCD 2013: 154-168 - [c57]Paul D. Franzon, Shivam Priyadarshi, Steve Lipa, W. Rhett Davis, Thorlindur Thorolfsson:
Exploring early design tradeoffs in 3DIC. ISCAS 2013: 545-549 - [c56]Shivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis, Paul D. Franzon:
Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors. ISQED 2013: 1-7 - [c55]Paul D. Franzon:
MOOCs, OOCs, flips and hybrids: The new world of higher education. MSE 2013: 13 - 2012
- [j25]Ting Zhu, Michael B. Steer, Paul D. Franzon:
Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits. IEEE Des. Test 29(6): 74-83 (2012) - [j24]Yi Lou, Zhuo Yan, Fan Zhang, Paul D. Franzon:
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods. J. Electron. Test. 28(1): 27-38 (2012) - [j23]Shivam Priyadarshi, T. Robert Harris, Samson Melamed, Carlos Tadeo Ortega Otero, Nikhil Kriplani, Carlos E. Christoffersen, Rajit Manohar, Steven R. Dooley, W. Rhett Davis, Paul D. Franzon, Michael B. Steer:
Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels. IET Circuits Devices Syst. 6(1): 35-44 (2012) - [j22]Samson Melamed, Thorlindur Thorolfsson, T. Robert Harris, Shivam Priyadarshi, Paul D. Franzon, Michael B. Steer, W. Rhett Davis:
Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 676-689 (2012) - [j21]Shivam Priyadarshi, Christopher S. Saunders, Nikhil Kriplani, Harun Demircioglu, W. Rhett Davis, Paul D. Franzon, Michael B. Steer:
Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1522-1535 (2012) - [c54]Thorlindur Thorolfsson, Steve Lipa, Paul D. Franzon:
A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integration. CICC 2012: 1-4 - [c53]Mustafa Berke Yelten, Paul D. Franzon, Michael B. Steer:
Process mismatch analysis based on reduced-order models. ISQED 2012: 648-655 - [c52]Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul D. Franzon:
A novel double floating-gate unified memory device. VLSI-SoC 2012: 53-58 - [c51]Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul D. Franzon:
Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates. VLSI-SoC (Selected Papers) 2012: 217-233 - 2011
- [j20]Daniel Schinke, Neil Di Spigna, M. Shiveshwarkar, Paul D. Franzon:
Computing with Novel Floating-Gate Devices. Computer 44(2): 29-36 (2011) - [j19]Daniel Schinke, Shivam Priyadarshi, W. Shepherd Pitts, Neil Di Spigna, Paul D. Franzon:
SPICE-compatible physical model of nanocrystal floating gate devices for circuit simulation. IET Circuits Devices Syst. 5(6): 477-483 (2011) - [j18]Thorlindur Thorolfsson, Nariman Moezzi Madani, Paul D. Franzon:
Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor. IET Comput. Digit. Tech. 5(3): 198-204 (2011) - [c50]Paul D. Franzon, W. Rhett Davis, Zheng Zhou, Shivam Priyadarshi, Matthew Hogan, Tanay Karnik, Ganapti Srinavas:
Coordinating 3D designs: Interface IP, standards or free form? 3DIC 2011: 1-3 - [c49]Shivam Priyadarshi, Jianchen Hu, Won Ha Choi, Samson Melamed, Xi Chen, W. Rhett Davis, Paul D. Franzon:
Pathfinder 3D: A flow for system-level design space exploration. 3DIC 2011: 1-8 - [c48]Ran Wang, Gary Charles, Paul D. Franzon:
Modeling and compare of through-silicon-via (TSV) in high frequency. 3DIC 2011: 1-6 - [c47]Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson, Samson Melamed:
3D Specific Systems: Design and CAD. Asian Test Symposium 2011: 470-473 - [c46]Daniel Schinke, Wallace Shep Pitts, Neil Di Spigna, Paul D. Franzon:
Low power interconnect design for fpgas with bidirectional wiring using nanocrystal floating gate devices (abstract only). FPGA 2011: 277 - [c45]Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson, Samson Melamed:
3D specific systems design and CAD. ICSAMOS 2011: 326-329 - [c44]Ting Zhu, Mustafa Berke Yelten, Michael B. Steer, Paul D. Franzon:
Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models. SIMULTECH (Selected Papers) 2011: 255-269 - [c43]Ting Zhu, Mustafa Berke Yelten, Michael B. Steer, Paul D. Franzon:
Application of Surrogate Modeling in Variation-aware Macromodel and Circuit Design. SIMULTECH 2011: 502-508 - [p1]Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson:
Design and Computer Aided Design of 3DIC. 3D Integration for NoC-based SoC Architectures 2011: 75-88 - 2010
- [j17]Thorlindur Thorolfsson, Samson Melamed, W. Rhett Davis, Paul D. Franzon:
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration. ACM Trans. Design Autom. Electr. Syst. 16(1): 5:1-5:25 (2010) - [c42]Paul D. Franzon, John M. Wilson, Ming Li:
Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications. 3DIC 2010: 1-4 - [c41]Steve Lipa, Thorlindur Thorolfsson, Paul D. Franzon:
The NCSU Tezzaron design kit. 3DIC 2010: 1-15 - [c40]Thorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon:
Logic-on-logic 3D integration and placement. 3DIC 2010: 1-4 - [c39]Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson:
Creating 3D specific systems: Architecture, design and CAD. DATE 2010: 1684-1688
2000 – 2009
- 2009
- [j16]William Rhett Davis, Eun Chu Oh, Ambarish M. Sule, Paul D. Franzon:
Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 496-506 (2009) - [j15]Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1267-1274 (2009) - [c38]Samson Melamed, Thorlindur Thorolfsson, Adi Srinivasan, Edmund Cheng, Paul D. Franzon, William Rhett Davis:
Junction-level thermal extraction and simulation of 3DICs. 3DIC 2009: 1-7 - [c37]Eun Chu Oh, Paul D. Franzon:
Technology impact analysis for 3D TCAM. 3DIC 2009: 1-5 - [c36]Thorlindur Thorolfsson, Samson Melamed, Gary Charles, Paul D. Franzon:
Comparative analysis of two 3D integration implementations of a SAR processor. 3DIC 2009: 1-4 - [c35]Menglin Tsai, Amy Klooz, Alexander Leonard, Jennie Appel, Paul D. Franzon:
Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC. 3DIC 2009: 1-8 - [c34]Ting Zhu, Paul D. Franzon:
An enhanced macromodeling approach for differential output drivers. BMAS 2009: 54-59 - [c33]Thorlindur Thorolfsson, Kiran Gonsalves, Paul D. Franzon:
Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study. DAC 2009: 51-56 - [c32]Thorlindur Thorolfsson, Nariman Moezzi Madani, Paul D. Franzon:
A low power 3D integrated FFT engine using hypercube memory division. ISLPED 2009: 231-236 - 2008
- [j14]Yuan Xie, Jason Cong, Paul D. Franzon:
Editorial: Special issue on 3D integrated circuits and microarchitectures. ACM J. Emerg. Technol. Comput. Syst. 4(4): 15:1-15:2 (2008) - [c31]Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul D. Franzon, Andrew Yang, Stephen V. Kosonocky:
Keeping hot chips cool: are IC thermal problems hot air? DAC 2008: 634-635 - [c30]Paul D. Franzon, W. Rhett Davis, Michael B. Steer, Steve Lipa, Eun Chu Oh, Thorlindur Thorolfsson, Samson Melamed, Sonali Luniya, Tad Doxsee, Stephen Berkeley, Ben Shani, Kurt Obermiller:
Design and CAD for 3D integrated circuits. DAC 2008: 668-673 - 2007
- [j13]Mehmet Rasit Yuce, Wentai Liu, John Damiano, Bhaskar Bharath, Paul D. Franzon, Numan Sadi Dogan:
SOI CMOS Implementation of a Multirate PSK Demodulator for Space Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(2): 420-431 (2007) - [j12]Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 231-236 (2007) - [c29]Eun Chu Oh, Paul D. Franzon:
Design Considerations and Benefits of Three-Dimensional Ternary Content Addressable Memory. CICC 2007: 591-594 - [c28]Ullas Pazhayaveetil, Dhruba Chandra, Paul D. Franzon:
Flexible Low Power Probability Density Estimation Unit For Speech Recognition. ISCAS 2007: 1117-1120 - [c27]Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franzon:
Hardware Architecture of a Parallel Pattern Matching Engine. ISCAS 2007: 1369-1372 - [c26]James E. Stine, Ivan D. Castellanos, Michael H. Wood, Jeff Henson, Fred Love, W. Rhett Davis, Paul D. Franzon, Michael Bucher, Sunil Basavarajaiah, Julie Oh, Ravi Jenkal:
FreePDK: An Open-Source Variation-Aware Design Kit. MSE 2007: 173-174 - 2006
- [j11]Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Paul D. Franzon:
3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver. IEEE J. Solid State Circuits 41(1): 287-296 (2006) - [c25]Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling. CICC 2006: 265-268 - [c24]Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, Evan Erickson, Paul D. Franzon:
A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver. CICC 2006: 773-776 - [c23]Sachin Sonkusale, Paul D. Franzon:
Controlled nanowire fabrication by PEDAL process. Nano-Net 2006: 1-8 - [c22]Dhruba Chandra, Ullas Pazhayaveetil, Paul D. Franzon:
Architecture for Low Power Large Vocabulary Speech Recognition. SoCC 2006: 25-28 - 2005
- [j10]W. Rhett Davis, John M. Wilson, Stephen E. Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael B. Steer, Paul D. Franzon:
Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Des. Test Comput. 22(6): 498-510 (2005) - [j9]Monther Aldwairi, Thomas M. Conte, Paul D. Franzon:
Configurable string matching hardware for speeding up intrusion detection. SIGARCH Comput. Archit. News 33(1): 99-107 (2005) - [c21]Liang Zhang, John M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon:
Driver pre-emphasis techniques for on-chip global buses. ISLPED 2005: 186-191 - [c20]Numan Sadi Dogan, Paul D. Franzon, Wentai Liu:
Impact of an SoC Research Project on Microelectronics Education: A Case Study. MSE 2005: 33-34 - [c19]Paul D. Franzon, David Nackashi, Christian Amsinck, Neil Di Spigna, Sachin Sonkusale:
Molecular Electronics - Devices and Circuits Technology. VLSI-SoC 2005: 1-10 - 2004
- [c18]Mehmet R. Yuce, Wentai Liu, Bhaskar Bharath, John Damiano, Paul D. Franzon:
The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers. CICC 2004: 591-594 - [c17]Liang Zhang, Wentai Liu, Rizwan Bashirullah, John M. Wilson, Paul D. Franzon:
Simplified delay design guidelines for on-chip global interconnects. ACM Great Lakes Symposium on VLSI 2004: 29-32 - [c16]J. A. Palmer, James F. Mulling, Brian Dessent, Edward Grant, Jeffrey W. Eischen, Alexei Gruverman, A. I. Kingon, Paul D. Franzon:
The Design, Fabrication, and Characterization of Millimeter Scale Motors for Miniature Direct Drive Robots. ICRA 2004: 4668-4673 - 2003
- [j8]Mircea R. Stan, Paul D. Franzon, Seth Copen Goldstein, John C. Lach, Matthew M. Ziegler:
Molecular electronics: from devices and interconnect to circuits and architecture. Proc. IEEE 91(11): 1940-1957 (2003) - [c15]Mehmet R. Yuce, Wentai Liu, John Damiano, Bhaskar Bharath, Paul D. Franzon, Numan Sadi Dogan:
A low power PSK receiver for space applications in 0.35-μm SOI CMOS. CICC 2003: 155-158 - 2002
- [j7]Pronita Mehrotra, Paul D. Franzon:
Novel hardware architecture for fast address lookups. IEEE Commun. Mag. 40(11): 66-71 (2002) - [c14]Stephen E. Mick, John M. Wilson, Paul D. Franzon:
4 Gbps high-density AC coupled interconnection. CICC 2002: 133-140 - [c13]Pronita Mehrotra, Paul D. Franzon:
Binary search schemes for fast IP lookups. GLOBECOM 2002: 2005-2009 - 2001
- [c12]Andreas Kuehlmann, Robert W. Dutton, Paul D. Franzon, Seth Copen Goldstein, Philip Luekes, Eric Parker, Thomas N. Theis:
Will Nanotechnology Change the Way We Design and Verify Systems? (Panel). ICCAD 2001: 174
1990 – 1999
- 1999
- [c11]B. E. Duewer, John M. Wilson, D. A. Winick, Paul D. Franzon:
MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications. ARVLSI 1999: 369-377 - [c10]Paul D. Franzon, Mark Basel, Aki Fujimara, Sharad Mehrotra, Ron Preston, Robin C. Sarma, Marty Walker:
Parasitic Extraction Accuracy - How Much is Enough? DAC 1999: 429 - [c9]Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte:
Dynamically Programmable Cache Evaluation and Virtualization. FPGA 1999: 246 - [c8]Toby Schaffer, Andy Stanaski, Alan Glaser, Paul D. Franzon:
The NCSU Cadence Design Kit for IC Fabrication through MOSIS. MSE 1999: 88-89 - 1997
- [j6]Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III:
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews. J. VLSI Signal Process. 16(2-3): 131-147 (1997) - [c7]Mir Azam, Paul D. Franzon, Wentai Liu:
Low power data processing by elimination of redundant computations. ISLPED 1997: 259-264 - 1995
- [j5]Robert J. Evans, Paul D. Franzon:
Energy consumption modeling and optimization for SRAM's. IEEE J. Solid State Circuits 30(5): 571-579 (1995) - [c6]Sharad Mehrotra, Paul D. Franzon, Michael B. Steer:
Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs. DAC 1995: 381-387 - 1994
- [j4]Sha Ma, Paul D. Franzon:
Energy control and accurate delay estimation in the design of CMOS buffers. IEEE J. Solid State Circuits 29(9): 1150-1153 (1994) - [c5]Sharad Mehrotra, Paul D. Franzon, Wentai Liu:
Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits. DAC 1994: 36-40 - 1993
- [j3]Paul D. Franzon, Robert J. Evans:
A Multichip Module Design Process for Notebook Computers. Computer 26(4): 41-49 (1993) - [c4]Slobodan Simovich, Paul D. Franzon, Michael B. Steer:
A simple method for noise tolerance characterization of digital circuits. Great Lakes Symposium on VLSI 1993: 52-56 - [c3]Todd A. Cook, Paul D. Franzon, Edwin A. Harcourt, Thomas K. Miller III:
System-Level Specification of Instruction Sets. ICCD 1993: 552-557 - 1992
- [c2]Ajay Dholakia, T. M. Lee, Donald L. Bitzer, Mladen A. Vouk, L. Wang, Paul D. Franzon:
An efficient table-driven decoder for one-half rate convolutional codes. ACM Southeast Regional Conference 1992: 116-123 - [c1]Paul D. Franzon, Slobodan Simovich, Michael B. Steer, Mark Basel, Sharad Mehrotra, Tom Mills:
Tools to Aid in Wiring Rule Generation for High Speed Interconnects. DAC 1992: 466-471 - 1990
- [j2]David E. van den Bout, Paul D. Franzon, John J. Paulos, Thomas K. Miller III, Wesley E. Snyder, H. Troy Nagle, Wentai Liu:
Scalable VLSI implementations for neural networks. J. VLSI Signal Process. 1(4): 367-385 (1990)
1980 – 1989
- 1987
- [j1]Stuart K. Tewksbury, Mehdi Hatamian, Paul D. Franzon, Larry A. Hornak, Curtis A. Siller Jr., Victor B. Lawrence:
FIR digital filters for high sample rate applications. IEEE Commun. Mag. 25(7): 62-72 (1987)
Coauthor Index
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