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ORCIDJosé Luis Huertas
José L. Huertas
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2010 – 2019
- 2016
[c65]Andrés Maldonado, Gloria Huertas, Adoración Rueda
, José Luis Huertas, Pablo Pérez, Alberto Yufera:
Cell-culture measurements using voltage oscillations. LASCAS 2016: 235-238- 2015
- [j31]Gloria Huertas, Andrés Maldonado, Alberto Yufera, Adoración Rueda, José Luis Huertas:
The Bio-Oscillator: A Circuit for Cell-Culture Assays. IEEE Trans. Circuits Syst. II Express Briefs 62-II(2): 164-168 (2015) - [c64]Andrés Maldonado, Pablo Pérez, Gloria Huertas, Alberto Yufera, Adoración Rueda, José L. Huertas:
From voltage oscillations to tissue-impedance measurements. BioCAS 2015: 1-4 - 2012
- [c63]Manuel J. Barragan Asian, Gildas Léger, José L. Huertas:
OBT for settling error test of sampled-data systems using signal-dependent clocking. ETS 2012: 1-6 - [c62]Manuel J. Barragan Asian, Gildas Léger, José Luis Huertas:
Multi-condition alternate test of analog, mixed-signal, and RF systems. LATW 2012: 1-6 - 2011
- [j30]Manuel J. Barragan Asian, Rafaella Fiorelli, Gildas Léger, Adoración Rueda, José L. Huertas:
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures. J. Electron. Test. 27(3): 277-288 (2011) - [c61]Manuel J. Barragan Asian, Rafaella Fiorelli, Gildas Léger, Adoración Rueda, José L. Huertas:
Improving the Accuracy of RF Alternate Test Using Multi-VDD Conditions: Application to Envelope-Based Test of LNAs. Asian Test Symposium 2011: 359-364 - 2010
- [c60]Manuel J. Barragan Asian, Gloria Huertas, Adoración Rueda, José Luis Huertas:
(Some) Open Problems to Incorporate BIST in Complex Heterogeneous Integrated Systems. DELTA 2010: 8-13 - [c59]Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas:
Low-cost signature test of RF blocks based on envelope response analysis. ETS 2010: 55-60
2000 – 2009
- 2009
- [c58]Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas:
A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis. Asian Test Symposium 2009: 255-260 - 2008
- [c57]Gloria Huertas, José Luis Huertas:
Oscillation-Based Test in Data Converters: On-Line Monitoring. DELTA 2008: 322-325 - [c56]Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías, Diego Vázquez, Adoración Rueda, José Luis Huertas:
A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. SBCCI 2008: 70-75 - 2007
- [c55]John M. Espinosa-Duran, Jaime Velasco-Medina, Gloria Huertas, José L. Huertas:
Total Ionizing Dose Effects in Switched-Capacitor Filters using Oscillation-Based Test. ICECS 2007: 841-844 - [c54]John M. Espinosa-Duran, Jaime Velasco-Medina, Gloria Huertas, José Luis Huertas:
Total ionizing dose effects in switched-capacitor filters using oscillation-based test. SBCCI 2007: 263-266 - 2005
- [j29]Adoración Rueda, Michel Renovell, José Luis Huertas:
Guest Editorial. J. Electron. Test. 21(3): 203 (2005) - [j28]Diego Vázquez, Gloria Huertas, África Luque, Manuel J. Barragan Asian, Gildas Léger, Adoración Rueda, José Luis Huertas:
Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST. J. Electron. Test. 21(3): 221-232 (2005) - [j27]Francisco Serra-Graells, José Luis Huertas:
Low-Voltage CMOS subthreshold log-domain filtering. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 2090-2100 (2005) - [c53]Maria J. Avedillo, José M. Quintana, José L. Huertas:
Robust frequency divider based on resonant tunneling devices. ISCAS (3) 2005: 2647-2650 - 2004
- [j26]Francisco Serra-Graells, Lluís Gómez, José Luis Huertas:
A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip. IEEE J. Solid State Circuits 39(8): 1271-1281 (2004) - [j25]Gildas Léger, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(1): 140-150 (2004) - [c52]Diego Vázquez, Gildas Léger, Gloria Huertas, Adoración Rueda, José L. Huertas:
A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications. DATE 2004: 298-305 - [c51]Marcelo Lubaszewski, José Luis Huertas:
Test and Design-for-Test of Mixed-Signal Integrated Circuits. IFIP Congress Tutorials 2004: 183-212 - [c50]José Luis Huertas:
Test and design-for-test of mixed-signal integrated circuits. SBCCI 2004: 4 - 2003
- [j24]Francisco Serra-Graells, José Luis Huertas:
Sub-1-V CMOS proportional-to-absolute temperature references. IEEE J. Solid State Circuits 38(1): 84-88 (2003) - [j23]Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas:
Oscillation-based test in bandpass oversampled A/D converters. Microelectron. J. 34(10): 927-936 (2003) - 2002
- [j22]Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
Practical Oscillation-Based Test of Integrated Filters. IEEE Des. Test Comput. 19(6): 64-72 (2002) - [j21]Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell. IEEE Des. Test Comput. 19(6): 73-82 (2002) - [j20]Manuel Martínez, Maria José Avedillo, José M. Quintana, José Luis Huertas:
COPAS: A New Algorithm for the Partial Input Encoding Problem. VLSI Design 14(2): 171-181 (2002) - [c49]Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas:
Practical Oscillation-Based Test in Analog Integrated Filters: Experimental Results. DELTA 2002: 18-24 - [c48]Diego Vázquez, Gloria Huertas, Gildas Léger, Adoración Rueda, José L. Huertas:
Practical solutions for the application of the oscillation-based-test in analog integrated circuits. ISCAS (1) 2002: 589-592 - [c47]José M. Quintana, Maria J. Avedillo, José L. Huertas:
Simplified Reed-Muller expressions for residue threshold functions. ISCAS (4) 2002: 599-602 - [c46]Diego Vázquez, Gloria Huertas, Adoración Rueda, Gildas Léger, José L. Huertas:
Low-cost on-chip measurements for Oscillation-Based-Test in Analog Integrated Circuits. LATW 2002: 89-93 - [c45]Diego Vázquez, Gloria Huertas, Gildas Léger, Adoración Rueda, José L. Huertas:
Practical Solutions for the Application of the Oscillation-Based-Test: Start-Up and On-Chip Evaluation. VTS 2002: 433-438 - 2001
- [j19]José M. Quintana, Maria J. Avedillo, José Luis Huertas:
Efficient Realization of a Threshold Voter for Self-Purging Redundancy. J. Electron. Test. 17(1): 69-73 (2001) - [j18]Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. J. Electron. Test. 17(5): 373-383 (2001) - [c44]Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
Structural testing of pipelined analog to digital converters. ISCAS (1) 2001: 436-439 - [c43]Eduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas:
Self-Testable Pipelined ADC with Low Hardware Overhead. VTS 2001: 272-278 - 2000
- [c42]Chin-Long Wey, Adam Osseiran, José Luis Huertas, Yeon-Chen Nieu:
Mixed-Signal SoC Testing: Is Mixed-Signal Design-for-Test on Its Way. Asian Test Symposium 2000: 15 - [c41]Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
Testing mixed-signal cores: practical oscillation-based test in an analog macrocell. Asian Test Symposium 2000: 31-38 - [c40]Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas:
A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. DATE 2000: 534-538 - [c39]Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas:
VHDL-based behavioural description of pipeline ADCs. ISCAS 2000: 681-684 - [c38]Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
Alternative DFT Strategies for High-Speed Pipelined Data Converters. LATW 2000: 123-127 - [c37]Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas:
Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell. VLSI Design 2000: 568-571
1990 – 1999
- 1999
- [j17]T. A. García, Antonio J. Acosta, J. M. Mora, J. Ramos, José Luis Huertas:
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. J. Electron. Test. 15(1-2): 115-127 (1999) - [c36]Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas:
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. DATE 1999: 521-525 - [c35]Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas:
Effective oscillation-based test for application to a DTMF filter bank. ITC 1999: 549-555 - 1998
- [j16]Diego Vázquez, Adoración Rueda, José Luis Huertas, Eduardo J. Peralías:
A high-Q bandpass fully differential SC filter with enhanced testability. IEEE J. Solid State Circuits 33(7): 976-986 (1998) - [c34]Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas:
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. DATE 1998: 810-814 - [c33]Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas:
A Dynamic Model for the State Assignment Problem. DATE 1998: 835-839 - [c32]Juan A. Prieto, Adoración Rueda, Ian Andrew Grout, Eduardo J. Peralías, José L. Huertas, Andrew Mark David Richardson:
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. DATE 1998: 905-909 - [c31]Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
CMOS pipelined A/D converters with concurrent error detection capability. ICECS 1998: 437-440 - [c30]Eduardo J. Peralías, Adoración Rueda, Juan A. Prieto, José L. Huertas:
DfT and on-line test of high-performance data converters: a practical case. ITC 1998: 534-540 - [c29]T. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos:
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. VTS 1998: 92-97 - 1997
- [j15]Iluminada Baturone, Santiago Sánchez-Solano, Angel Barriga, José Luis Huertas:
Implementation of CMOS fuzzy controllers as mixed-signal integrated circuits. IEEE Trans. Fuzzy Syst. 5(1): 1-19 (1997) - [c28]Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas:
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. DAC 1997: 281-286 - [c27]Juan A. Prieto, Adoración Rueda, José M. Quintana, José Luis Huertas:
A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. ED&TC 1997: 389-394 - [c26]Bozena Kaminska, Karim Arabi, I. Bell, José L. Huertas, Bruce C. Kim, Adoración Rueda, Mani Soma, Prashant Goteti:
Analog and Mixed-Signal Benchmark Circuits-First Release. ITC 1997: 183-190 - [c25]Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
A DFT Technique for Analog-to-Digital Converters with digital correction. VTS 1997: 302-307 - 1996
- [j14]José L. Huertas, Santiago Sánchez-Solano, Iluminada Baturone, Angel Barriga:
Integrated circuit implementation of fuzzy controllers. IEEE J. Solid State Circuits 31(7): 1051-1058 (1996) - [c24]Diego Vázquez, José L. Huertas, Adoración Rueda:
Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design. VTS 1996: 42-47 - 1995
- [j13]Maria J. Avedillo, José M. Quintana, José Luis Huertas:
Constrained state assignment of easily testable FSMs. J. Electron. Test. 6(1): 133-138 (1995) - [j12]Fernando Medeiro, Belén Pérez-Verdú, Ángel Rodríguez-Vázquez, José L. Huertas:
A vertically integrated tool for automated design of ΣΔ modulators. IEEE J. Solid State Circuits 30(7): 762-772 (1995) - [j11]Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas:
SODS: a new CMOS differential-type structure. IEEE J. Solid State Circuits 30(7): 835-838 (1995) - [j10]Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano:
Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44(12): 1456-1461 (1995) - [c23]José M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas:
Optimum PLA folding through boolean satisfiability. ASP-DAC 1995 - [c22]Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas:
New CMOS VLSI linear self-timed architectures. ASYNC 1995: 14-23 - [c21]Eduardo J. Peralías, Adoración Rueda, José Luis Huertas:
Statistical behavioral modeling and characterization of A/D converters. ICCAD 1995: 562-566 - [c20]R. Rodriguez-Macias, Francisco V. Fernández, Ángel Rodríguez-Vázquez, José L. Huertas:
A Tool for Fast Mismatch Analysis of Analog Circuits. ISCAS 1995: 2148-2151 - [c19]Diego Vázquez, Adoración Rueda, José L. Huertas:
A solution for the on-line test of analog ladder filters. VTS 1995: 48-53 - 1994
- [j9]Alberto Yúfera, Adoración Rueda, José L. Huertas:
Programmable switched-current wave analog filters. IEEE J. Solid State Circuits 29(8): 927-935 (1994) - [c18]Diego Vázquez, Adoración Rueda, José L. Huertas:
A Low-Cost Strategy for Testing Analog Filters. ISCAS 1994: 123-126 - [c17]Alberto Yufera, Adoración Rueda, José L. Huertas:
A Study of the Sensitivity of Switched-Current Wave Analog Filters to Mismatching and Clock-Feedthrough Errors. ISCAS 1994: 317-320 - [c16]Fernando Medeiro, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez, José L. Huertas:
Modeling OpAmp-Induced Harmonic Distorition for Switched-Capacitor Sigma-Delta Modulator Design. ISCAS 1994: 445-448 - [c15]Juan A. Prieto, José M. Quintana, Adoración Rueda, José L. Huertas:
An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits. ISCAS 1994: 491-494 - [c14]Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, José Luis Huertas:
A Real Time Clustering CMOS Neural Engine. NIPS 1994: 755-762 - [c13]Diego Vázquez, Adoración Rueda, José Luis Huertas:
A new strategy for testing analog filters. VTS 1994: 36-41 - 1993
- [j8]José Luis Huertas, Adoración Rueda, Diego Vázquez:
Improving the testability of switched-capacitor filters. J. Electron. Test. 4(4): 299-313 (1993) - [j7]Bernabé Linares-Barranco, Edgar Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José L. Huertas:
A CMOS analog adaptive BAM with on-chip learning and weight refreshing. IEEE Trans. Neural Networks 4(3): 445-455 (1993) - [c12]Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas:
Modeling of real bistables in VHDL. EURO-DAC 1993: 460-465 - [c11]Servando Espejo-Meana, Ángel Rodríguez-Vázquez, Rafael Domínguez-Castro, Bernabé Linares-Barranco, José Luis Huertas:
A Model for VLSI Implementation of CNN Image Processing Chips Using Current-mode Techniques. ISCAS 1993: 970-973 - [c10]Fernando Medeiro, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez, José L. Huertas:
A Tool for Automated Design of Sigma-Delta Modulators Using Statistical Optimization. ISCAS 1993: 1373-1376 - [c9]Maria J. Avedillo, José M. Quintana, José L. Huertas:
Easily Testable PLA-based FSMS. ISCAS 1993: 1603-1606 - [c8]Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro:
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS 1993: 2019-2022 - 1992
- [j6]Adoración Rueda, José L. Huertas:
Testability in analogue cellular neural networks. Int. J. Circuit Theory Appl. 20(5): 583-587 (1992) - [c7]Francisco V. Fernández, Ángel Rodríguez-Vázquez, J. D. Martín, José L. Huertas:
Accuate simplification of large symbolic formulae. ICCAD 1992: 318-321 - [c6]José Luis Huertas, Diego Vázquez, Adoración Rueda:
On-line testing of switched-capacitor filters. VTS 1992: 102-106 - 1991
- [c5]Bernabé Linares-Barranco, Edgar Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José Luis Huertas:
CMOS Continuous BAM With On Chip Learning. IWANN 1991: 322-327 - 1990
- [j5]José L. Huertas, Belén Pérez-Verdú, Ángel Rodríguez-Vázquez:
Analysis and design of self-limiting single-OP-AMPRC oscillators. Int. J. Circuit Theory Appl. 18(1): 53-69 (1990) - [c4]Maria J. Avedillo, José M. Quintana, José Luis Huertas:
A new method for the state reduction of incompletely specified finite sequential machines. EURO-DAC 1990: 552-556
1980 – 1989
- 1988
- [j4]Belén Pérez-Verdú, José L. Huertas, Ángel Rodríguez-Vázquez:
A new nonlinear time-domain op-amp macromodel using threshold functions and digitally controlled network elements. IEEE J. Solid State Circuits 23(4): 959-971 (1988) - [c3]José L. Huertas, José M. Quintana:
A new method for the efficient state-assignment of PLA-based sequential machines. ICCAD 1988: 156-159 - 1987
- [j3]Ángel Rodríguez-Vázquez, José L. Huertas, Adoración Rueda, Belén Pérez-Verdú, Leon O. Chua:
Chaos from switched-capacitor circuits: Discrete maps. Proc. IEEE 75(8): 1090-1106 (1987)
1970 – 1979
- 1978
- [c2]José Luis Huertas, José I. Acha, L. Macias:
On the synthesis of multivalued circuits using principally binary elements. MVL 1978: 32 - [c1]José Luis Huertas, José I. Acha, G. Sanchez Gomez:
Theory and design of multivalued memory elements. MVL 1978: 213-220 - 1976
- [j2]José L. Huertas, José I. Acha:
Self-Synchronization of Asynchronous Sequential Circutis Employing a General Clock Function. IEEE Trans. Computers 25(3): 297-300 (1976) - [j1]José I. Acha, José L. Huertas:
On Input and Next-State Equations of the R-S Type M-Stable. IEEE Trans. Computers 25(7): 759-763 (1976)
Coauthor Index
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