"CAD for Delay Optimization of Symmetrical FPGA Architecture through Hybrid ..."

Sunil Kr. Singh et al. (2012)

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DOI: 10.1007/978-3-642-31600-5_57

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-25

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Sunil Kr. Singh, R. K. Singh, M. P. S. Bhatia, Saurabh P. Singh:
CAD for Delay Optimization of Symmetrical FPGA Architecture through Hybrid LUTs/PLAs. ACITY (3) 2012: 581-591

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