"FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters."

Qiang Liu, HanJing Qian (2017)

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DOI: 10.1109/FCCM.2017.16

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Qiang Liu, HanJing Qian:
FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters. FCCM 2017: 29

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