"Power and Delay Efficient Hardware Implementation with ATPG for Vedic ..."

Anchit Arun et al. (2023)

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DOI: 10.1145/3628454.3631153

access: closed

type: Conference or Workshop Paper

metadata version: 2023-12-13

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Anchit Arun, Ananya Chakraborty, Priyanka Dutta, Debajyoti Pal, Tridibesh Nag, Debasis De, Sudip Ghosh, Hafizur Rahaman:
Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra. IAIT 2023: 23:1-23:6

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