"Multilayer VLSI Layout for Interconnection Networks."

Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz Parhami (2000)

> Home

Details and statistics

DOI: 10.1109/ICPP.2000.876069

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/icpp/YehVP00
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icpp/YehVP00
Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz Parhami:
Multilayer VLSI Layout for Interconnection Networks. ICPP 2000: 33-42

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.