"A two-port SRAM for real-time video processor saving 53% of bitline power ..."

Hidehiro Fujiwara et al. (2006)

> Home

Details and statistics

DOI: 10.1145/1165573.1165589

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/islped/FujiwaraNMMMKY06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/islped/FujiwaraNMMMKY06
Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.