"4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor."

Penny Li et al. (2015)

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DOI: 10.1109/ISSCC.2015.7062931

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister:
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. ISSCC 2015: 1-3

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