"An 8MB level-3 cache in 32nm SOI with column-select aliasing."

Don Weiss et al. (2011)

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DOI: 10.1109/ISSCC.2011.5746309

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-04

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Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu:
An 8MB level-3 cache in 32nm SOI with column-select aliasing. ISSCC 2011: 258-260

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