"A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture ..."

Chun Shiah et al. (2019)

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DOI: 10.23919/VLSIC.2019.8778049

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-05

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Chun Shiah, C. N. Chang, Richard Crisp, C. P. Lin, C. N. Pan, C. P. Chuang, H. L. Chen, S. H. Jheng, T. F. Chang, W. J. Huang, K. C. Ting, Rick Dai, W. M. Huang, Bor-Doou Rong, Nicky Lu:
A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems. VLSI Circuits 2019: 116-

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