"A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection ..."

Akihide Sai et al. (2016)

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DOI: 10.1109/JSSC.2016.2603993

access: closed

type: Journal Article

metadata version: 2020-08-30

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Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura:
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. IEEE J. Solid State Circuits 51(12): 3125-3136 (2016)

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