"A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS."

Viki Szortyka et al. (2015)

> Home

Details and statistics

DOI: 10.1109/JSSC.2015.2442998

access: closed

type: Journal Article

metadata version: 2020-10-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/SzortykaSRPKW15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/SzortykaSRPKW15
Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais, Maarten Kuijk, Piet Wambacq:
A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS. IEEE J. Solid State Circuits 50(9): 2025-2036 (2015)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.