"Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing ..."

Sudarshan Bahukudumbi, Krishnendu Chakrabarty (2009)

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DOI: 10.1109/TCAD.2008.2009150

access: closed

type: Journal Article

metadata version: 2022-01-03

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Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 111-120 (2009)

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