"Graph-Constrained Sparse Performance Modeling for Analog Circuit ..."

Jun Tao et al. (2019)

> Home

Details and statistics

DOI: 10.1109/TCAD.2018.2848590

access: closed

type: Journal Article

metadata version: 2020-09-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/TaoSZZL19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/TaoSZZL19
Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1385-1398 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.