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ORCID47th DAC 2010: Anaheim, CA, USA
- Sachin S. Sapatnekar:
Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010. ACM 2010, ISBN 978-1-4503-0002-5
Panel
- Ruchir Puri, William H. Joyner, Raj Jammy, Ahmed Jerraya, Jan M. Rabaey, Walden C. Rhines, Leon Stok:
EDA challenges and options: investing for the future. 1-2
Special session: Post-silicon validation or avoiding the $50 million paperweight
- Jagannath Keshava, Nagib Hakim, Chinna Prudvi:
Post-silicon validation challenges: how EDA and academia can help. 3-7 - John Goodenough, Rob Aitken:
Post-silicon is too late avoiding the $50 million paperweight starts with validated designs. 8-11 - Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici:
Post-silicon validation opportunities, challenges and recent advances. 12-17
Speed up your model! RTL, data-flow, or SystemC
- Chia-Jui Hsu, José Luis Pino, Fei-Jiang Hu:
A mixed-mode vector-based dataflow approach for modeling and simulating LTE physical layer. 18-23 - Nicola Bombieri
, Franco Fummi, Graziano Pravadelli:
Abstraction of RTL IPs into embedded software. 24-29 - Scott Sirowy, Chen Huang, Frank Vahid:
Online SystemC emulation acceleration. 30-35
Embedded software timing matters!
- Jilong Kuang, Laxmi N. Bhuyan:
LATA: a latency and throughput-aware packet processing system. 36-41 - Thorsten Zitterell, Christoph Scholl:
A probabilistic and energy-efficient scheduling approach for online application in real-time systems. 42-47 - Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty:
Timing analysis of esterel programs on general-purpose multiprocessors. 48-51 - Lijuan Luo, Martin D. F. Wong, Wen-mei W. Hwu:
An effective GPU implementation of breadth-first search. 52-55
Thermal tracking, monitoring and characterization
- Abdullah Nazma Nowroz, Ryan Cochran, Sherief Reda:
Thermal monitoring of real processors: techniques for sensor allocation and full characterization. 56-61 - Ryan Cochran, Sherief Reda:
Consistent runtime thermal prediction and control through workload phase detection. 62-67 - Yufu Zhang, Ankur Srivastava:
Adaptive and autonomous thermal tracking for high performance computing systems. 68-73
Advanced clock design and flip-chip layout
- Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis:
Non-uniform clock mesh optimization with linear programming buffer insertion. 74-79 - Xin-Wei Shih, Yao-Wen Chang:
Fast timing-model independent buffered clock-tree synthesis. 80-85 - Ying-Yu Chen, Chen Dong, Deming Chen:
Clock tree synthesis under aggressive buffer insertion. 86-89 - Xiaodong Liu, Yifan Zhang, Gary K. Yeap, Chunlei Chu, Jian Sun, Xuan Zeng:
Global routing and track assignment for flip-chip designs. 90-93
Panel
- Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor:
Bridging pre-silicon verification and post-silicon validation. 94-95
Special session: Virtualization in the embedded systems: where do we go?
- Christian Bertin, Christophe Guillon, Koen De Bosschere:
Compilation and virtualization in the HiPEAC vision. 96-101 - Albert Cohen, Erven Rohou:
Processor virtualization and split compilation for heterogeneous multicore embedded systems. 102-107 - Sung-Min Lee, Sang-Bum Suh, Jong-Deok Choi:
Fine-grained I/O access control based on Xen virtualization for 3G/4G mobile devices. 108-113 - Johan Fornaeus:
Device hypervisors. 114-119
Memory and multiprocessor design space exploration
- Giovanni Mariani, Aleksandar Brankovic, Gianluca Palermo, Jovana Jovic, Vittorio Zaccaria, Cristina Silvano:
A correlation-based design space exploration methodology for multi-processor systems-on-chip. 120-125 - Jishen Zhao, Xiangyu Dong, Yuan Xie:
Cost-aware three-dimensional (3D) many-core multiprocessor design. 126-131 - Chenjie Yu, Peter Petrov:
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms. 132-137 - Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun:
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. 138-143
Interconnect networks: present and future
- Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel H. Loh, Alok N. Choudhary:
Quantifying and coping with parametric variations in 3D-stacked microarchitectures. 144-149 - Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li:
Cost-driven 3D integration with interconnect layers. 150-155 - Xiang Zhang, Ahmed Louri:
A multilayer nanophotonic interconnection network for on-chip many-core communications. 156-161 - Young-Jin Yoon, Nicola Concer, Michele Petracca, Luca P. Carloni:
Virtual channels vs. multiple physical networks: a comparative analysis. 162-165 - Mehdi Modarressi, Hamid Sarbazi-Azad, Arash Tavakkol:
An efficient dynamically reconfigurable on-chip network architecture. 166-169
Core techniques in formal verification
- Florian Pigorsch, Christoph Scholl:
An AIG-Based QBF-solver using SAT for preprocessing. 170-175 - Max Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Jörg Bormann, Wolfgang Kunz:
Analyzing k-step induction to compute invariants for SAT-based property checking. 176-181 - Hana Chockler, Daniel Kroening, Mitra Purandare:
Coverage in interpolation-based model checking. 182-187 - Olivier Coudert:
An efficient algorithm to verify generalized false paths. 188-193
New frontiers in routing
- Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth:
A parallel integer programming approach to global routing. 194-199 - Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
Multi-threaded collision-aware global routing with bounded-length maze routing. 200-205 - Jin-Tai Yan, Zhi-Wei Chen:
Two-sided single-detour untangling for bus routing. 206-211 - Hui Kong, Qiang Ma, Tan Yan, Martin D. F. Wong:
An optimal algorithm for finding disjoint rectangles and its application to PCB routing. 212-217
Panel
- Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger:
Who solves the variability problem? 218-219
Special session: Joint DAC/IWBDA special session engineering biology: fundamentals and applications
- Marc D. Riedel, Soha Hassoun, Ron Weiss, Pamela Silver, J. Christopher Anderson, Richard M. Murray:
Joint DAC/IWBDA special session engineering biology: fundamentals and applications. 220-221
Reliability and integrity of circuits and systems
- Sheng Wei, Saro Meguerdichian, Miodrag Potkonjak:
Gate-level characterization: foundations and hardware security applications. 222-227 - Peter Lisherness, Kwang-Ting (Tim) Cheng:
SCEMIT: a systemc error and mutation injection tool. 228-233 - Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich:
Towards scalable system-level reliability analysis. 234-239
Embedded hardware for security, data type refinement, and arbitration
- Ryan Helinski, Dhruva Acharyya, Jim Plusquellic:
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. 240-243 - Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner:
Theoretical analysis of gate level information flow tracking. 244-247 - David Novo, Min Li, Robert Fasthuber, Praveen Raghavan, Francky Catthoor:
Exploiting finite precision information to guide data-flow mapping. 248-253 - Adam B. Kinsman, Nicola Nicolici:
Robust design methods for hardware accelerators for iterative algorithms in scientific computing. 254-257 - Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang:
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. 258-261
Statistical techniques for silicon-to-model correlation
- Wangyang Zhang, Xin Li, Rob A. Rutenbar:
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. 262-267 - Luís Guerra e Silva, Joel R. Phillips, L. Miguel Silveira:
Speedpath analysis under parametric timing models. 268-273 - Lin Xie, Azadeh Davoodi, Kewal K. Saluja:
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. 274-279
Placement: from traditional techniques to novel circuit styles
- Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang:
Pulsed-latch aware placement for timing-integrity optimization. 280-285 - Minsik Cho, Haoxing Ren, Hua Xiang, Ruchir Puri:
History-based VLSI legalization using network flow. 286-291 - Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang:
Performance-driven analog placement considering boundary constraint. 292-297
Panel
- Samta Bansal, Juan C. Rey, Andrew Yang, Myung-Soo Jang, L. C. Lu, Philippe Magarshack, Pol Marchal, Riko Radojcic:
3-D stacked die: now or future? 298-299
Special session: A decade of NOC research - where do we stand?
- Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini:
Networks on Chips: from research to products. 300-305 - Kees Goossens, Andreas Hansson:
The aethereal network on chip after ten years: goals, evolution, lessons, and future. 306-311 - Bruce Mathewson:
The evolution of SOC interconnect and how NOC fits within it. 312-313
Exploiting concurrency for system-level performance
- Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam:
Automatic multithreaded pipeline synthesis from transactional datapath specifications. 314-319 - Raj R. Nadakuditi, Igor L. Markov:
On the costs and benefits of stochasticity in stream processing. 320-325 - Lin Huang, Qiang Xu:
Performance yield-driven task allocation and scheduling for MPSoCs under process variation. 326-331 - Andreas Schranzhofer, Rodolfo Pellizzoni, Jian-Jia Chen, Lothar Thiele, Marco Caccamo:
Worst-case response time analysis of resource access models in multi-core systems. 332-337
Data Access Times Define Performance!
- Guangdeng Liao, Heeyeol Yu, Laxmi N. Bhuyan:
A new IP lookup cache for high performance IP routers. 338-343 - Yun Liang, Tulika Mitra:
Instruction cache locking using temporal reuse profile. 344-349 - Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Yi He, Meikang Qiu, Edwin Hsing-Mean Sha:
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. 350-355 - Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. 356-361
Tools for effective post-silicon validation and test
- Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski:
Fully X-tolerant, very high scan compression. 362-367 - Sung-Boem Park, Anne Bracy, Hong Wang, Subhasish Mitra:
BLoG: post-silicon bug localization in processors using bug localization graphs. 368-373 - Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir:
Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. 374-379 - Michael A. Kochte, Marcel Schaal, Hans-Joachim Wunderlich, Christian G. Zoellin:
Efficient fault simulation on many-core processors. 380-385
Shapes and statistics: manufacturability and yield
- Lin Xie, Azadeh Davoodi:
Representative path selection for post-silicon timing prediction under variability. 386-391 - Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Ren, Lei He:
QuickYield: an efficient global-search based parametric yield estimation with performance constraints. 392-397 - Yen-Hung Lin, Yih-Lang Li:
Double patterning lithography aware gridless detailed routing with innovative conflict graph. 398-403 - Kanak Agarwal:
Frequency domain decomposition of layouts for double dipole lithography. 404-407 - Yongchan Ban, David Z. Pan:
Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography. 408-411
Panel
- Andreas Kuehlmann, Raul Camposano, James Colgan, John Chilton, Samuel George, Rean Griffith, Paul Leventis, Deepak Singh:
Does IC design have a future in the clouds? 412-414
Special session: The analog model crisis - how can we solve it?
- Bradley N. Bond, Luca Daniel:
Automated compact dynamical modeling: an enabling tool for analog designers. 415-420 - Kenneth S. Kundert, Henry Chang:
Model-based functional verification. 421-424 - Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao:
Fortifying analog models with equivalence checking and coverage analysis. 425-430
Application-driven network-on-chip design
- Colin J. Ihrig, Rami G. Melhem, Alex K. Jones:
Automated modeling and emulation of interconnect designs for many-core chip multiprocessors. 431-436 - Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam:
Trace-driven optimization of networks-on-chip configurations. 437-442 - Jason Cong, Chunyue Liu, Glenn Reinman:
ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. 443-448 - Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng:
NTPT: on the end-to-end traffic prediction in the on-chip networks. 449-452 - Wooyoung Jang, David Z. Pan:
Application-aware NoC design for efficient SDRAM access. 453-456
Exploiting FPGA-specific features for robustness and efficiency
- Kaveh Elizeh, Nicola Nicolici:
Embedded memory binding in FPGAs. 457-462 - Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic:
RAMP gold: an FPGA-based architecture simulator for multiprocessors. 463-468 - Manu Jose, Yu Hu, Rupak Majumdar, Lei He:
Rewiring for robustness. 469-474
Leakage estimation and optimization
- Mingzhi Gao, Zuochang Ye, Yan Wang, Zhiping Yu:
Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis. 475-480 - Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong:
A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation. 481-486 - Jun Seomun, Insup Shin, Youngsoo Shin:
Synthesis and implementation of active mode power gating circuits. 487-492 - Heng Yu, Bharadwaj Veeravalli, Yajun Ha:
Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems. 493-498
Logic synthesis is alive and kicking
- Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang:
BooM: a decision procedure for boolean matching with abstraction and dynamic learning. 499-504 - Yung-Chih Chen, Chun-Yao Wang:
Node addition and removal in the presence of don't cares. 505-510 - Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu:
ECR: a low complexity generalized error cancellation rewiring scheme. 511-516 - Jason Cong, Kirill Minkovich:
LUT-based FPGA technology mapping for reliability. 517-522
Panel
- Nagaraj Ns, John Byler, Koorosh Nazifi, Venugopal Puvvada, Toshiyuki Saito, Alan Gibbons, S. Balajee:
What's cool for the future of ultra low power designs? 523-524
Special session: Design closure for reliability
- Brian W. Thompto, Bodo Hoppe:
Verification for fault tolerance of the IBM system z microprocessor. 525-530 - Natasa Miskov-Zivanov, Diana Marculescu:
Formal modeling and reasoning for reliability analysis. 531-536 - Kypros Constantinides, Todd M. Austin:
Using introspective software-based testing for post-silicon debug and repair. 537-542
Energy-efficient embedded hardware design and management
- Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal:
Xetal-Pro: an ultra-low energy and high throughput SIMD processor. 543-548 - Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor:
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms. 549-554 - Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar:
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. 555-560
Parallel and efficient techniques in circuit simulation
- Xiaoji Ye, Peng Li:
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation. 561-566 - Yong Zhang, Peng Li, Garng M. Huang:
Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis. 567-572 - Xuexin Liu, Hao Yu, Sheldon X.-D. Tan:
A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs. 573-578
Thermal management and optimization
- Yang Ge, Parth Malani, Qinru Qiu:
Distributed task migration for thermal management in many-core systems. 579-584 - Sushu Zhang, Karam S. Chatha:
Thermal aware task sequencing on embedded processors. 585-590 - Jieyi Long, Seda Ogrenci Memik:
A framework for optimizing thermoelectric active cooling systems. 591-596
Catch of the day in benchmarking and optimal synthesis
- Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma:
Eyecharts: constructive benchmarking of gate sizing heuristics. 597-602 - Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn:
Detecting tangled logic structures in VLSI netlists. 603-608 - Mustafa Altun, Marc D. Riedel:
Lattice-based computation of Boolean functions. 609-612 - Jason Thong, Nicola Nicolici:
A novel optimal single constant multiplication algorithm. 613-616
Panel
- Arkadeb Ghosal, Paolo Giusto, Alberto L. Sangiovanni-Vincentelli, Joseph D'Ambrosio, Ed Nuckolls, Harald Wilhelm, Jim Tung, Markus Kuhl, Peter van Staa:
Education panel: designing the always connected car of the future. 617-618
Special session: WACI: wild and crazy ideas
- Chen-Ling Chou, Anca M. Miron, Radu Marculescu:
Find your flow: increasing flow experience by designing "human" embedded systems. 619-620 - Andrew DeOrio, Valeria Bertacco:
Electronic design automation for social networks. 621-622 - Azalia Mirhoseini, Yousra Alkabani, Farinaz Koushanfar:
Real time emulations: foundation and applications. 623-624 - Cristinel Ababei:
Network on chip design and optimization using specialized influence models. 625-626 - Dean Truong, Bevan M. Baas:
Circuit modeling for practical many-core architecture design exploration. 627-628 - Farinaz Koushanfar:
Hierarchical hybrid power supply networks. 629-630 - Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong:
Detachable nano-carbon chip with ultra low power. 631-632 - Miodrag Potkonjak:
Synthesis of trustable ICs using untrusted CAD tools. 633-634
Algorithms and architectures for emerging technologies
- Yang Zhao, Krishnendu Chakrabarty:
Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips. 635-640 - Cliff Chiung-Yu Lin, Yao-Wen Chang:
Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips. 641-646 - Robert Wille, Mathias Soeken, Rolf Drechsler:
Reducing the number of lines in reversible circuits. 647-652 - Oleg Golubitsky, Sean M. Falconer, Dmitri Maslov:
Synthesis of the optimal 4-bit reversible circuits. 653-656 - Yiyuan Xie, Mahdi Nikdast, Jiang Xu, Wei Zhang, Qi Li, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Weichen Liu:
Crosstalk noise and bit error rate analysis for optical network-on-chip. 657-660
Simulation and modeling techniques for devices and interconnect
- Zhuo Feng, Zhiyu Zeng:
Parallel multigrid preconditioning on graphics processing units (GPUs) for robust power grid analysis. 661-666 - Tarek A. El-Moselhy, Luca Daniel:
Stochastic dominant singular vectors method for variation-aware extraction. 667-672 - Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Closed-form modeling of layout-dependent mechanical stress. 673-678 - Sanda Lefteriu, Jan Mohring:
Generating parametric models from tabulated data. 679-682 - Yuanzhe Wang, Chi-Un Lei, Grantham K. H. Pang, Ngai Wong:
MFTI: matrix-format tangential interpolation for modeling multi-port systems. 683-686
Design of ultra low-power systems
- Bingjun Xiao, Yiyu Shi, Lei He:
A universal state-of-charge algorithm for batteries. 687-692 - Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys:
A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. 693-698 - Adam C. Cabe, Zhenyu Qi, Mircea R. Stan:
Stacking SRAM banks for ultra low power standby mode operation. 699-704 - Weixun Wang, Prabhat Mishra:
PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme. 705-710
Variation-aware methods for SRAMs and clocks
- Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark:
In-situ characterization and extraction of SRAM variability. 711-716 - Paul Zuber, Petr Dobrovolný, Miguel Miranda:
A holistic approach for statistical SRAM analysis. 717-722 - Tak-Yung Kim, Taewhan Kim:
Clock tree synthesis with pre-bond testability for 3D stacked IC designs. 723-728 - Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang:
An efficient phase detector connection structure for the skew synchronization system. 729-734
Joint user track panel: What will make your next design experience a much better one?
- Thomas Harms, Juan-Antonio Caraballo, Reynold D'Sa, Ruud A. Haring, Derek Urbaniak, Guntram Wolski, James You:
What will make your next design experience a much better one? 730
Special session: Cyber-physical systems demystified
- Ragunathan Rajkumar, Insup Lee, Lui Sha, John A. Stankovic:
Cyber-physical systems: the next computing revolution. 731-736 - Edward A. Lee:
CPS foundations. 737-742 - Insup Lee, Oleg Sokolsky:
Medical cyber physical systems. 743-748 - Jan Kleissl, Yuvraj Agarwal:
Cyber-physical energy systems: focus on smart buildings. 749-754
Application and improvement of dynamic verification
- Wenchao Li, Alessandro Forin, Sanjit A. Seshia:
Scalable specification mining for verification and diagnosis. 755-760 - Bo D. Wang, Yuhao Zhu, Yangdong Deng:
Distributed time, conservative parallel logic simulation on GPUs. 761-766 - ByongChan Lim, Jaeha Kim, Mark A. Horowitz:
An efficient test vector generation for checking analog/mixed-signal functional models. 767-772 - Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi, Kaustav Guha:
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent. 773-776 - Morteza Fayyazi, Laurent Kirsch:
Efficient simulation of oscillatory combinational loops. 777-780
Timing analysis and circuit optimization for novel technologies and DFM
- Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu:
Transistor sizing of custom high-performance digital circuits with parametric yield considerations. 781-786 - Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
RDE-based transistor-level gate simulation for statistical static timing analysis. 787-792 - Vineeth Veetil, Yung-Hsu Chang, Dennis Sylvester, David T. Blaauw:
Efficient smart monte carlo based SSTA on graphics processing units with improved resource utilization. 793-798 - Chao-Hsuan Hsu, Chester Liu, En-Hua Ma, James Chien-Mo Li:
Static timing analysis for flexible TFT circuits. 799-802 - Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan:
TSV stress aware timing analysis with applications to 3D-IC layout optimization. 803-806
System power modeling and management
- Gaurav Dhiman, Kresimir Mihic, Tajana Rosing:
A system for online power prediction in virtualized environments using Gaussian mixture models. 807-812 - Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley Mao:
Performance and power modeling in a multi-programmed multi-core environment. 813-818 - Ranjani Sridharan, Rabi N. Mahapatra:
Reliability aware power management for dual-processor real-time embedded systems. 819-824 - Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Recovery-driven design: a power minimization methodology for error-tolerant processor modules. 825-830
Management of power integrity and circuit reliability
- Zhiyu Zeng, Xiaoji Ye, Zhuo Feng, Peng Li:
Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation. 831-836 - Xuanxing Xiong, Jia Wang:
An efficient dual algorithm for vectorless power grid verification under linear current constraints. 837-842 - Xueqian Zhao, Yonghe Guo, Zhuo Feng, Shiyan Hu:
Parallel hierarchical cross entropy optimization for on-chip decap budgeting. 843-848 - Zhenyu Qi, Jiajing Wang, Adam C. Cabe, Stuart N. Wooters, Travis N. Blalock, Benton H. Calhoun, Mircea R. Stan:
SRAM-based NBTI/PBTI sensor system design. 849-852 - Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
A statistical simulation method for reliability analysis of SRAM core-cells. 853-856
Panel
- Daniel Gajski, Todd M. Austin, Steve Svoboda:
What input-language is the best choice for high level synthesis (HLS)? 857-858
Special session: Computing without guarantees
- Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones:
Stochastic computation. 859-864 - Srimat T. Chakradhar, Anand Raghunathan:
Best-effort computing: re-thinking parallel software and hardware. 865-870 - Melvin A. Breuer:
Hardware that produces bounded rather than exact results. 871-876
Design and modeling of technologies beyond CMOS
- Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie:
Impact of process variations on emerging memristor. 877-882 - Sansiri Tanachutiwat, Ji Ung Lee, Wei Wang, Chun Yung Sung:
Reconfigurable multi-function logic based on graphene P-N junctions. 883-888 - Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra:
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. 889-892 - Hamed F. Dadgour, Muhammad Mustafa Hussain, Casey Smith, Kaustav Banerjee:
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. 893-896
Yield-aware optimization and modeling for analog circuits
- Wangyang Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xin Li:
Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression. 897-902 - Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu:
Behavior-level yield enhancement approach for large-scaled analog circuits. 903-908 - Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa:
Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances. 909-912 - Amith Singhee, Pamela Castalino:
Pareto sampling: choosing the right weights by derivative pursuit. 913-916
Reducing the cost of test
- Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu:
An error tolerance scheme for 3D CMOS imagers. 917-922 - Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu:
Fast identification of operating current for toggle MRAM by spiral search. 923-928 - Leyi Yin, Peng Li:
Exploiting reconfigurability for low-cost in-situ test and monitoring of digital PLLs. 929-934
Special session: Smart power: from your cell phone to your home
- Johnny John, Chris Riddle:
Smart phone power. 935-936 - Ian A. Hiskens:
What's smart about the smart grid? 937-939 - Eli Chiprout:
On-die power grids: the missing link. 940-945
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