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ORCID12th DDECS 2009: Liberec, Czech Republic
- Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic. IEEE Computer Society 2009, ISBN 978-1-4244-3341-4
Invited Talks
- Georges G. E. Gielen:
Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS. 1 - Abhijit Chatterjee:
Cognitive self-adaptive computing and communication systems: Test, control and adaptation. 2 - Anton Chichkov:
Challenges for test and design for test. 3
Poster Session I
- Brendan Mullane
, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann:
An SOC platform for ADC test and measurement. 4-7 - Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus:
A scheme of logic self repair including local interconnects. 8-11 - Farhad Alibeygi Parsan, Ahmad Ayatollahi, Adib Abrishamifar:
Investigating the linearity of MOSFET-only switched-capacitor DeltaSigma modulators under low-voltage condition. 12-15 - Juraj Brenkus, Viera Stopjaková, Ronny Vanhooren, Anton Chichkov:
Comparison of different test strategies on a mixed-signal circuit. 16-19 - Elke De Mulder, Wim Aerts, Bart Preneel, Ingrid Verbauwhede, Guy A. E. Vandenbosch:
Case Study : A class E power amplifier for ISO-14443A. 20-23 - Jinpeng Zhao, Qiang Zhou, Yici Cai:
Fast congestion-aware timing-driven placement for island FPGA. 24-27 - Hong-Yi Huang, Fu-Chien Tsai:
Analysis and optimization of ring oscillator using sub-feedback scheme. 28-29 - Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou:
Improve clock gating through power-optimal enable function selection. 30-33 - Stefan Kolodzinski, Edward Hrynkiewicz:
An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions. 34-37
ATPG and Fault Simulation Techniques
- Daniel Tille, Rolf Drechsler:
A fast untestability proof for SAT-based ATPG. 38-43 - Davide Bresolin, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Tiziano Villa:
The impact of EFSM composition on functional ATPG. 44-49 - Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda:
An efficient fault simulation technique for transition faults in non-scan sequential circuits. 50-55
Asynchronous Circuit Design
- P. Balasubramanian, David A. Edwards, Charlie Brej:
Self-timed full adder designs based on hybrid input encoding. 56-61 - Thomas Panhofer, Werner Friesenbichler, Martin Delvai:
Optimization concepts for self-healing asynchronous circuits. 62-67 - Igor Lemberski, Petr Fiser:
Asynchronous two-level logic of reduced cost. 68-73
RF and High Speed Circuit Design
- Kurt Schweiger, Heimo Uhrmann, Horst Zimmermann:
Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS. 74-77 - Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz:
Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. 78-83 - Shyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee:
BIST assisted wideband digital compensation for MB-UWB transmitters. 84-89
Architecture and Symbolic RTL Synthesis
- Tomás Martínek, Jan Vozenilek, Matej Lexa:
Architecture model for approximate palindrome detection. 90-95 - Petr Kobierský, Jan Korenek, Libor Polcak:
Packet header analysis and field extraction for multigigabit networks. 96-101 - Stanislaw Deniziak, Mariusz Wisniewski:
A symbolic RTL synthesis for LUT-based FPGAs. 102-107
Memory Design and Test
- Yiorgos Sfikas, Yiorgos Tsiatouhas:
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. 108-113 - Thomas Reinbacher, Martin Horauer, Bastian Schlich:
Using 3-valued memory representation for state space reduction in embedded assembly code model checking. 114-119
Poster Session II
- Olivier Ginez, Jean-Michel Portal, Hassen Aziza:
An on-line testing scheme for repairing purposes in Flash memories. 120-123 - Martin Donoval, Martin Daricek, Juraj Marek, Viera Stopjaková:
Power devices current monitoring using horizontal and vertical magnetic force sensor. 124-127 - Kunihiro Asada, Taku Sogabe, Toru Nakura, Makoto Ikeda:
Measurement of power supply noise tolerance of self-timed processor. 128-131 - Yun-Che Wen:
Test scheme for switched-capacitor circuits by digital analyses. 132-135 - Martin Rozkovec, Ondrej Novák:
Structural test of programmed FPGA circuits. 136-139 - Yngvar Berg, Omid Mirmotahari:
Low voltage precharge CMOS logic. 140-143 - Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz:
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. 144-147 - Gábor Marosy, Zoltán Kovács, Gyula Horváth:
Effective mars rover platform design with Hardware / Software co-design. 148-151
Power Supply and Interconnect Related Faults
- Peter Tummeltshammer, Andreas Steininger:
On the role of the power supply as an entry for common cause faults - An experimental analysis. 152-157 - Florence Azaïs, Yves Bertrand, Michel Renovell:
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. 158-163 - Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka:
Effective BIST for crosstalk faults in interconnects. 164-169
Industrial Session
- Jiri Halak, Sven Ubik:
MTPP - Modular Traffic Processing Platform. 170-173 - Qing K. Zhu, Vincent Bars:
Simulation and planning method for on-chip power distribution - An industry perspective. 174-177 - Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko:
Experience in Virtual Testing of RSD cyclic A/D converters. 178-181 - Heimo Uhrmann, Franz Schlögl, Kurt Schweiger, Horst Zimmermann:
A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS. 182-185
Student Session: RF and High Speed Circuits
- Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng:
0.5V 160-MHz 260uW all digital phase-locked loop. 186-193 - Y. C. Chang, Hsuan-Ling Kao, C. H. Kao, C. H. Yang, Jeffrey S. Fu, Nemai C. Karmakar, Li-Chun Chang:
0.18 µm CMOS UWB LNA with new feedback configuration for optimization low noise, high gain and small area. 194-197
Student Session: Miscellaneous
- Jirí Giesl, Ladislav Behal, Karel K. Vlcek:
Hardware solution of chaos based image encryption. 198-201 - Miroslav Manik, Elena Gramatová:
Diagnosis of faulty units in regular graphs under the PMC model. 202-205 - Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. 206-209
Poster Session III
- András Timár, György Bognár:
Contactless characterization of MEMS devices using optical microscopy. 210-213 - Werner Friesenbichler, Thomas Panhofer, Martin Delvai:
A comprehensive approach for soft error tolerant Four State Logic. 214-217 - Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre:
High-level symbolic simulation for automatic model extraction. 218-221 - Piotr Jantos, Damian Grzechca, Jerzy Rutkowski:
Global parametric faults identification with the use of Differential Evolution. 222-225 - Charlie Brej, Doug Edwards:
Forward and backward guarding in early output logic. 226-229 - Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski:
Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories. 230-233 - Stanislaw Deniziak, Robert Tomaszewski:
Contention-avoiding custom topology generation for network-on-chip. 234-237 - Krzysztof Marcinek, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Enhanced LEON3 core for superscalar processing. 238-241
Analog Design and Sensors
- Yngvar Berg, Omid Mirmotahari:
Ultra low-voltage switched current mirror. 242-245 - Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila:
Self-timed thermal sensing and monitoring of multicore systems. 246-251 - Alberto Yufera, Adoración Rueda:
A CMOS bio-impedance measurement system. 252-257
Off-Line and On-Line Testing
- Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda:
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs. 258-263 - Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
Comprehensive bridging fault diagnosis based on the SLAT paradigm. 264-269 - Flavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan:
Round-level concurrent error detection applied to Advanced Encryption Standard. 270-275
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