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ORCIDIEEE Transactions on Computers, Volume 18
Volume 18, Number 1, January 1969
- Gwendolyn G. Hays:
Computer-Aided Design: Simulation of Digital Design Logic. 1-10 - Donald L. Dietmeyer, Yueh-Hsung Su:
Logic Design Automation of Fan-In Limited NAND Networks. 11-22 - Douglas C. Dorrough:
A Methodical Approach to Analyzing and Synthesizing a Self-Repairing Computer. 22-42 - Dennis J. Lynes:
High-Speed DC Coupled Digit Detector. 43-47 - Eugene L. Lawler, Karl N. Levitt, James Turner:
Module Clustering to Minimize Delay in Digital Networks. 47-57 - Yueh-Hsung Su, Donald L. Dietmeyer:
Computer Reduction of Two-Level, Multiple-Output Switching Circuits. 58-63 - Jack E. Shemer, Someshwar C. Gupta:
A Simplified Analysis of Processor "Look-Ahead" and Simultaneous Operation of a Multi-Module Main Memory. 64-71 - Peter M. Fenwick:
Binary Multiplication with Overlapped Addition Cycles. 71-74 - Donald Fraser:
Incrementing a Bit-Reversed Integer. 74 - Glen G. Langdon Jr.:
Subtraction by Minuend Complementation. 74-76 - Takayasu Ito:
Note on a Class of Statistical Recognition Functions. 76-79 - Paul H. Giroux:
Comment on "Generalized Parallel Redundancy in Digital Computers". 80 - Narsingh Deo:
Author's Reply3. 80 - T. A. Taebel:
Comment on "A Variable Counter Design Technique". 80
Volume 18, Number 2, February 1969
- Paul Lucas:
An Accumulator Chip. 105-114 - Amar Mukhopadhyay:
Unate Cellular Logic. 114-121 - Branislav Hrúz:
Unateness Test of a Boolean Function and Two General Synthesis Methods Using Threshold Logic Elements. - Giovanni B. Gerace, Giuseppe Gestri:
Sequential Machines with Less Delay Elements than Feedback Paths. 132-144 - Kung-Chi Wang:
Synthesis of Linear Sequential Machines with Unspecifed Outputs. 145-153 - Ying Huang Chuang:
Transition Logic Circuits and a Synthesis Method. 154-168 - Theo Jay Powell:
A Procedure for Selecting Diagnostic Tests. 168-175 - Glen G. Langdon Jr.:
Delay-Free Asynchronous Circuits with Constrained Line Delays. 175-181 - Iain D. G. Macleod:
Comments on "A High-Speed Algorithm for the Computer Generation of Fourier Transforms". 182 - E. C. Ogbuobiri:
Comment on "Solution of Nonlinear Equations". 182-183 - Walter L. Whipple:
Comments on "Higher-Radix Division Using Estimates of the Divisor and Partial Remainder". 183
Volume 18, Number 3, March 1969
- David H. O'Herren:
Radar Reflectivity Plots - Digital Method. 205-211 - Antonín Svoboda:
Decimal Adder with Signed Digit Arithmetic. 212-215 - Gary D. Hornbuckle, Richard N. Spann:
Diagnosis of Single-Gate Failures in Combinational circuits. 216-220 - Keinosuke Fukunaga, Thomas F. Krile:
Calculation of Bayes' Recognition Error for Two Multivariate Gaussian Distributions. 220-229 - Shimon Even, Albert R. Meyer
:
Sequential Boolean Equations. 230-240 - Karl S. Menger Jr.:
A Transform for Logic Networks. 241-250 - Harold S. Stone, Charles L. Jackson:
Structures of the Affine Families of Switching Functions. 251-257 - Chao-Wei Mow, King-Sun Fu:
Loop-Free Threshold Element Structures. 257-267 - Walter L. Whipple:
Calculation of Integrated Circuit Yields. 268 - Nick A. Farmer:
A Digital Comparator for Use with Computer Displays. 269-270 - Howard J. Quaife:
On (d, k, μ) Graphs. 270-272 - Peter Weiner, Ted A. Dolotta:
Mixed Memory Type Realizations of Sequential Machines. 272-277 - Virgil E. Vickers:
Comment on "Solution of Nonlinear Equations"1. 277 - Mehdi B. Kermani, Marlin H. Mickle, Lawrence P. McNamee:
Identification of Disjunctively Decomposable Logic Functions Employing a Karnaugh Map. 277-279 - Fred C. Davis:
Comment on "A Variable Counter Design Technique". 281 - Edward L. Renschler:
Author's Reply2. 281 - R. Jones:
Another Comment on "A Variable Counter Design Technique". 281-282 - Edward L. Renschler:
Author's reply2. 282-284
Volume 18, Number 4, April 1969
- James R. Duley, Donald L. Dietmeyer:
Translation of a DDL Digital System Specification to Boolean Equations. 305-313 - Dilip K. Banerji, Janusz A. Brzozowski:
Sign Detection in Residue Number Systems. 313-320 - H. Daniel Schnurmann, Klim Maling:
A Statistical Approach to the Computation of Delays in Logic Circuits. 320-328 - Subrata K. Das:
A Method of Decision Making in Pattern Recognition. 329-333 - Michael L. Dertouzos, Martin E. Kaliski, Kenneth P. Polzen:
On-Line Simulation of Block-Diagram Systems. 333-342 - Peter N. Marinos:
Fuzzy Logic and its Application to Switching Systems. 343-348 - Stephen N. Cole:
Real-Time Computation by n-Dimensional Iterative Arrays of Finite-State Machines. 349-365 - Arnold L. Knoll:
Experiments with "Characteristic Loci" for Recognition of Handprinted Characters. 366-372 - Robert O. Winder:
Threshold Gate Approximations Based on Chow Parameters. 372-375 - Alan B. Marcovitz, Charles M. Shub:
An Improved Algorithm for the Simplification of Switching Functions Using Unique Identifiers on a Karnaugh Map. 376-378 - Don Steinmeyer:
Logarithm Function Generated by Parallel Resistors. 379-381 - Frederick F. Sellers Jr., Mu Yue Hsiao, LeRoy W. Bearnson:
Correction to "Analyzing Errors with the Boolean Difference"1. 381
Volume 18, Number 5, May 1969
- John W. Sammon Jr.:
A Nonlinear Mapping for Data Structure Analysis. 401-409 - William T. Weeks:
Mathematical Analysis of Ferrite Core Memory Arrays. 409-416 - Carroll R. Hall, Stephen J. Kahne:
Automated Scaling for Hybrid Computers. 416-423 - N. K. Natarajan, Paul A. V. Thomas:
A Multiaccess Associative Memory. 424-428 - Frank O. Hadlock, Clarence L. Coates:
Realization of Sequential Machines with Threshold Elements. 428-439 - Shanker Singh:
Asynchronous Sequential Circuits with Feedback. 440-450 - Sukumar Ghosh, Dhruba Basu, Arun Kumar Choudhury:
Multigate Synthesis of General Boolean Functions by Threshold Logic Elements. 451-456 - John L. Shanks:
Computation of the Fast Walsh-Fourier Transform. 457-459 - Raymond M. Kline, Donald F. Wann:
Threshold Logic Design of Pulse-Type Sequential Networks. 459-465 - S. V. Dabadghao:
A Method for Finding Feedback Partitions for Sequential Machines. 465-467 - Gary K. Maki, James H. Tracey, Robert J. Smith:
Generation of Design Equations in Asynchronous Sequential Circuits. 467-472 - Celso de Renna e Souza:
A Theorem on the State Reduction of Synthesized Stochastic Machines. 473-474
Volume 18, Number 6, June 1969
- Robert Vichnevetsky:
Use of Functional Approximation Methods in the Computer Solution of Initial Value Partial Differential Equation Problems. 499-512 - Peter T. Rux:
A Glass Delay Line Content-Addressed Memory System. 512-520 - Louis J. Koczela, Gary Y. Wang:
The Design of a Highly Parallel Computer Organization. 520-529 - David F. Martin, Gerald Estrin:
Path Length Computations on Graph Models of Computations. 530-536 - Fabrizio Luccio:
Extending the Definition of Prime Compatibility Classes of States in Incomplete Sequential Machine Reduction. 537-540 - Arthur D. Friedman, Ronald L. Graham, Jeffrey D. Ullman:
Universal Single Transition Time Asynchronous State Assignments. 541-547 - Fred W. Smith:
Design of Multicategory Pattern Classifiers with Two-Category Classifier Design Procedures. 548-551 - Robert L. Cosgriff:
Multiplex Logic Circuits. 552-556 - George C. Sethares, John N. Pierce:
On the Generation of a Class of Multithreshold Functions. 557-559 - Richard C. Born:
Transformation of Ternary Switching Functions to Completely Symmetric Ternary Switching Functions. 559-560 - Robert B. McGhee:
Some Aids to the Detection of Hazards in Combinational Switching Circuits. 561-565 - Frank M. Brown:
Comment on "Canonical Programming of Nonlinear and Time-Varying Differential Equations". 566 - Martin Graham:
Error Correction in Batch-Fabricated Memories. 566-567 - K. S. Hall:
Modified Twisted-Ring Counter Circuit. 568 - Mitchell P. Marcus:
S-R-T Flip-Flop. 568-569
Volume 18, Number 7, July 1969
- Theodore D. Friedman, Sih-Chin Yang:
Methods Used in an Automatic Logic Design Generator (ALERT). 593-614 - Ernest G. Henrichon Jr., King-Sun Fu:
A Nonparametric Partitioning Procedure for Pattern Classification. 614-624 - C. Dennis Weiss:
The Characterization and Properties of Cascade Realizable Switching Functions. 624-633 - Celso de Renna e Souza, R. Jeffrey Leake:
Relationships Among Distinct Models and Notions of Equivalence for Stochastic Finite-State Systems. 633-641 - Peter Stucki:
Generation of Grey Tones by Computer for Simulation of Visual Information Systems. 642-643 - Alexander D. Hause, D. R. Weller:
A Variable-Length Code for an Incremental Display System. 643-644 - Jack E. Shemer, Someshwar C. Gupta:
On the Design of Bayesian Storage Allocation Algorithms for Paging and Segmentation. 644-651 - Abraham Lempel:
On k-Stable Feedback Shift Registers. 652-660 - Martin Cohn, Shimon Even:
The Design of Shift Register Generators for Finite Sequences. 660-662 - Martin Cohn, Shimon Even:
A Gray Code Counter. 662-664
Volume 18, Number 8, August 1969
- Merlin G. Smith, William A. Notz, Erwin Schischa:
The Questions of Systems Implementation with Large-Scale Integration. 690-694 - John H. Huttenhoff, Richard R. Shively:
Arithmetic Unit of a Computing Element in a Global, Highly Parallel Computer. 695-698 - Stanley A. White:
Digital Adaptive-Element Building Blocks for MOS Large-Scale Integration. 699-706 - Joseph O. Campeau:
The Block-Oriented Computer. 706-718 - William H. Kautz:
Cellular Logic-in-Memory Arrays. 719-727 - Charles W. Weller:
A High-Speed Carry Circuit for Binary Adders. 728-732 - Marcel J. E. Golay:
Hexagonal Parallel Pattern Transformations. 733-740 - Alan Dunworth, J. I. Roche:
The Error Characteristics of the Binary Rate Multiplier. 741-745 - Hans M. Aus, Granino A. Korn:
Table-Lookup/Interpolation Function Generation for Fixed-Point Digital Computations. 745-749 - John L. Douce, Timothy J. Healy:
Evaluation of the Amplitude Distribution of Quasi-Gaussian Signals Obtained From Pseudorandom Noise. 749-752 - William S. Meisel, R. Sohrab Kashef:
Hazards in Asynchronous Sequential Circuits. 752-759 - Thomas Francis Dwyer:
Comments on "Fault Testing and Diagnosis in Combinational Digital Circuits". 760 - William H. Kautz:
Author's Reply2. 760 - Glen G. Langdom Jr.:
Correction to "Subtraction by Minuend Complementation"l. 760
Volume 18, Number 9, September 1969
- Shu-Kwan Chan:
The Serial Solution of the Diffusion Equation Using Nonstandard Hybrid Techniques. 786-799 - Robert L. Davis:
The ILLIAC IV Processing Element. 800-816 - Samuel Cohen, Robert O. Winder:
Threshold Gate Building Blocks. 816-823 - Frederic J. Mowle:
Readily Programmable Procedures for the Analysis of Nonlinear Feedback Shift Registers. 824-829 - Chung-Jen Tan, Premachandran R. Menon, Arthur D. Friedman:
Structural Simplification and Decomposition of Asynchronous Sequential Circuits. 830-838 - C. Dennis Weiss:
Optimal Synthesis of Arbitrary Switching Functions with Regular Arrays of 2-Input 1-Output Switching Elements. 839-856 - K. Vairavan:
On the Lower Bound to the Memory of Finite State Machines. 856-861 - Angus R. Mckay:
Comment on "Computer-Aided Design: Simulation of Digital Design Logic". 862 - Gwendolyn G. Hays:
Author's Reply4. 862 - Charles H. Haspel:
Remarks on "Comments on 'An Algorithm for Synthesis of Multiple-Output Combinational Logic'". 863 - Edward S. Davidson, Gernot Metze:
Authors' Reply4. 863-864
Volume 18, Number 10, October 1969
- Wesley W. Chu:
Optimal File Allocation in a Multiple Computer System. 885-889 - Yao Tung Yen:
Computer-Aided Test Generation for Four-Phase MOS LSI Circuits. 890-894 - Helmut K. V. Lotsch:
Magnetic-Field Design Considerations for a Plated-Wire Memory. 894-899 - Albert Wolinsky:
Unified Interval Classification and Unified 3-Classification for Associative Memories. 899-911 - William S. Meisel:
Potential Functions in Mathematical Pattern Recognition. 911-918 - Harris Drucker:
Computer Optimization of Recognition Networks. 918-923 - H. R. Hwa, C. L. Sheng:
An Approach for the Realization of Threshold Functions of Order r. 923-939 - W. T. Lynch:
Worst-Case Analysis of a Resistor Memory Matrix. 940-942 - Edward G. Coffman Jr.:
On the Tradeoff Between Response and Preemption Costs in a Foreground-Background Computer Service Discipline. 942-947 - Domenico Ferrari, Antonio Grasselli:
A Cellular Structure for Sequential Networks. 947-953 - S. C. De Sarkar, A. K. Basu, Arun Kumar Choudhury:
Simplification of Incompletely Specified Flow Tables with the Help of Prime Closed Sets. 953-956 - Martin S. Schmookler:
On Mod-2 Sums of Products. 957 - Wayne A. Davis:
Logical Design Using Shift Registers. 958-960 - Domenico Ferrari:
Correction to "A Division Method Using a Parallel Multiplier". 960
Volume 18, Number 11, November 1969
- Edward A. Patrick, Frederic P. Fischer II:
Cluster Mapping with Experimental Computer Graphics. 987-991 - Joseph Abate, Harvey Dubner:
Optimizing the Performance of a Drum-Like Storage. 992-997 - Linus Schrage:
Analysis and Optimization of a Queueing Model of a Real-Time Computer Control System. 997-1003 - Robert M. Jones:
Factors Affecting the Efficiency of A Virtual Memory. 1004-1008 - Peter J. Denning:
Equipment Configuration in Balanced Computer Systems. 1008-1012 - Jean-Loup Baer, Gerald Estrin:
Bounds for Maxium Parallelism in a Bilogic Graph Model of Computations. 1012-1014 - Richard R. Muntz, Edward G. Coffman Jr.:
Optimal Preemptive Scheduling on Two-Processor Systems. 1014-1020 - Edward K. Bowdon Sr.:
Priority Assignment in a Network of Computers. 1021-1026 - James W. Jones Jr., Chester C. Carroll:
A Timed-Shared Digital Filter Realization. 1027-1030 - H. Blair Burner, Richard P. Million, Ottis W. Rechard, John S. Sobolewski:
A Programmable Data Concentrator for a Large Computing System. 1030-1038 - Ad J. van de Goor, C. Gordon Bell, Donald A. Witcraft:
Design and Behavior of TSS/8: a PDP-8 Based Time-Sharing System. 1038-1043 - Ad J. van de Goor, C. Gordon Bell:
A Control Unit for a DEC PDP-8 Computer and a Burroughs Disk. 1044-1048 - Peter I. P. Boulton, Pierce A. Reid:
A Process-Control Language. 1049-1053 - Isaak N. Samuel:
Synthesis and Analysis: A Flexible Technique for Processing Command Language. 1053-1061 - Francis F. Lee:
Study of "Look-Aside" Memory. 1062-1064 - Bruce E. Menn:
Digital Letdown Computer for Vertical Guidance. 1065-1068
Volume 18, Number 12, December 1969
- Ivan E. Sutherland:
A Method for Solving Arbitrary-Wall Mazes by Computer. 1092-1097 - Edward S. Davidson:
An Algorithm for NAND Decomposition Under Network Constraints. 1098-1109 - Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon:
Design of Asynchronous Circuits Assuming Unbounded Gate Delays. 1110-1120 - H. Allen Curtis:
Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part I. 1121-1127 - L. P. Bolgiano Jr., Michael J. Piovoso:
Relationship of Poisson Transform to Laguerre Expansions. 1128-1131 - William K. Pratt:
An Algorithm for a Fast Hadamard Matrix Transform of Order Twelve. 1131-1132 - Oliver Aberth:
A Multiple Computer Linkage. 1132-1134 - Julian R. Ullmann:
Experiments with the n-tuple Method of Pattern Recognition. 1135-1137 - W. E. Thomson:
Comment on "Solution of Nonlinear Equations". 1138 - James T. Taylo:
Note on "Solution of Nonlinear Equations". 1138-1140 - Marshall C. Y. Kuo:
Author's Reply. 1140-1142 - Theodore D. Friedman, S. C. Yang:
Correction to "Methods Used in an Automatic Logic Design Generator (ALERT)". 1142-1143
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