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ORCIDVLSI Design, Volume 2014
Volume 2014, 2014
- Xiaolong Ma
, Jiangtao Xu, Guican Chen:
Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers. 451310:1-451310:9 - Antony W. Savich, Shawki Areibi:
A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM). 712085:1-712085:11 - Yeong-Kang Lai, Yeong-Lin Lai, Thomas Schumann:
Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications. 761215:1-761215:2 - Syed Asad Alam, Oscar Gustafsson:
Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain. 217495:1-217495:14 - Shantanu Dutt, Dinesh P. Mehta, Gi-Joon Nam:
New Algorithmic Techniques for Complex EDA Problems. 134946:1-134946:2 - Daniel Llamocca, Marios S. Pattichis:
A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients. 651943:1-651943:24 - Khader Mohammad, Ahsan Kabeer, Tarek M. Taha:
On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding. 801241:1-801241:14 - Wafi Danesh, Jaya Dofe, Qiaoyan Yu:
Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic. 652187:1-652187:11 - Shahzad Asif, Yinan Kong:
Low-Area Wallace Multiplier. 343960:1-343960:6 - Marwan A. Jaber, Daniel Massicotte:
Radix-2α/4β Building Blocks for Efficient VLSI's Higher Radices Butterflies Implementation. 690594:1-690594:13 - C. John Moses, D. Selvathi, V. M. Anne Sophia:
VLSI Architectures for Image Interpolation: A Survey. 872501:1-872501:10 - S. Syed Ameer Abbas, S. J. Thiruvengadam, S. Susithra:
Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity. 825183:1-825183:15 - Kaiyu Wang, Qingxin Yan, Shihua Yu, Xianwei Qi, Yudi Zhou, Zhenan Tang:
High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos. 923618:1-923618:9 - Ran Xiao, Chunhong Chen:
Gate-Level Circuit Reliability Analysis: A Survey. 529392:1-529392:12 - Shikha Panwar, Mayuresh Piske, Aatreya Vivek Madgula:
Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits. 380362:1-380362:5 - Chi-Chia Sun, Jürgen Götze, Gene Eu Jan:
Parallel Jacobi EVD Methods on Integrated Circuits. 596103:1-596103:9 - Sahar Arshad, Muhammad Ismail, Usman Ahmad, Anees ul Husnain, Qaiser Ijaz:
Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design. 406416:1-406416:7 - Deepa Yagain, A. Vijaya Krishna:
Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool. 280701:1-280701:18 - Trong-Yen Lee, Chi-Han Huang:
Design of Smart Power-Saving Architecture for Network on Chip. 531653:1-531653:10 - Yu-Cheng Fan, Chih-Kang Lin, Shih-Ying Chou, Chun-Hung Wang, Shu-Hsien Wu, Hung-Kuan Liu:
Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design. 698041:1-698041:5 - Reza Faghih Mirzaee, Keivan Navi, Nader Bagherzadeh:
High-Efficient Circuits for Ternary Addition. 534587:1-534587:15 - Vadim Geurkov, Lev Kirischian:
On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing. 465907:1-465907:8 - Christopher Bailey, Brendan Mullane:
Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics. 493189:1-493189:13 - Yu-Cheng Fan, Qiaoyan Yu, Thomas Schumann, Ying-Ren Chien, Chih-Cheng Lu:
Advanced VLSI Architecture Design for Emerging Digital Systems. 746132:1-746132:2
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