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ORCIDEldar Zianbetov
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2020 – today
- 2020
[j2]Mehdi Terosiet, Eldar Zianbetov, Farouk Vallette, Marie-Minerve Louërat, Patrick Garda, Dimitri Galayko, Sylvain Feruglio
:
A comprehensive in-depth study of tri-state inverter based DCO. Microelectron. J. 99: 104760 (2020)
2010 – 2019
- 2019
- [j1]Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard:
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1673-1677 (2019) - 2016
- [c15]Eugene Koskin, Elena Blokhina, Chuan Shan, Eldar Zianbetov, Orla Feely, Dimitri Galayko:
Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks. NEWCAS 2016: 1-4 - 2015
- [c14]Eldar Zianbetov, Edith Beigné, Gregory di Pendina:
Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology. ASYNC 2015: 139-146 - [c13]Edith Beigné, Jean-Frédéric Christmann, Eldar Zianbetov, Gregory di Pendina:
Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing. ECCTD 2015: 1-4 - [c12]Jeremy Lopes, Gregory di Pendina, Eldar Zianbetov, Edith Beigné, Lionel Torres:
Radiative Effects on MRAM-Based Non-Volatile Elementary Structures. ISVLSI 2015: 321-326 - [c11]Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko:
A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. NEWCAS 2015: 1-4 - 2014
- [c10]Dimitri Galayko, Elena Blokhina, Eldar Zianbetov, Andrii Dudka, François Anceau, Éric Colinet, Anton Korniienko, Jérôme Juillard, Philippe Basset:
Complexity in heterogeneous systems on chips: Dsign and analysis challenges. ISCAS 2014: 1997-2000 - [c9]Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov:
"Swimming pool"-like distributed architecture for clock generation in large many-core SoC. ISCAS 2014: 2768-2771 - [c8]Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov:
A reconfigurable distributed architecture for clock generation in large many-core SoC. ReCoSoC 2014: 1-8 - 2013
- [c7]Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard:
Distributed clock generator for synchronous SoC using ADPLL network. CICC 2013: 1-4 - [c6]Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko:
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. ReConFig 2013: 1-6 - 2011
- [c5]Jean-Michel Akre, Jérôme Juillard, Mohammad Javidan, Eldar Zianbetov, Dimitri Galayko, Anton Korniienko, Éric Colinet:
A design approach for networks of Self-Sampled All-Digital Phase-Locked Loops. ECCTD 2011: 725-728 - [c4]Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard:
FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FPT 2011: 1-4 - [c3]Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Éric Colinet, Jérôme Juillard:
A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors. ISCAS 2011: 2577-2580 - [c2]Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, Éric Colinet, Gérard Scorletti, Jean-Michel Akre, Jérôme Juillard:
All-digital PLL array provides reliable distributed clock for SOCs. ISCAS 2011: 2589-2592 - [c1]Eldar Zianbetov, François Anceau, Mohammad Javidan, Dimitri Galayko, Éric Colinet, Jérôme Juillard:
A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation. ISCAS 2011: 2845-2848
Coauthor Index
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