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Hiroyuki Usui
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2020 – today
- 2023
- [j10]Hiroyuki Usui:
Automatic measurement of building setbacks and streetscape widths and their spatial variability along streets and in plots: integration of streetscape skeletons and plot geometry. Int. J. Geogr. Inf. Sci. 37(4): 810-838 (2023) - [j9]Hiroyuki Usui:
Simulation of urban perforation after random vacant plot generation: application of the thinning point process. Int. J. Geogr. Inf. Sci. 37(6): 1264-1287 (2023) - 2022
- [j8]Hiroyuki Usui, Yasushi Asami, Ikuho Yamada:
A normative model to estimate the number of persons not social distancing in a 3D complex built space. Int. J. Geogr. Inf. Sci. 36(3): 617-637 (2022) - 2020
- [j7]Hiroyuki Usui, Akihiro Teraki, Kei-ichi Okunuki, Toshiaki Satoh:
A comparison of neighbourhood relations based on ordinary Delaunay diagrams and area Delaunay diagrams: an application to define the neighbourhood relations of buildings. Int. J. Geogr. Inf. Sci. 34(11): 2177-2203 (2020) - [c6]Joan Perez, Alexandre Ornon, Hiroyuki Usui:
Variography and Morphometry for Classifying Building Centroids: Protocol, Data and Script. ICCSA (4) 2020: 415-424
2010 – 2019
- 2019
- [j6]Hiroyuki Usui:
A bottom-up approach for delineating urban areas minimizing the connection cost of built clusters: Comparison with top-down-based densely inhabited districts. Comput. Environ. Urban Syst. 77 (2019) - 2018
- [j5]Hiroyuki Usui, Yasushi Asami:
Size distribution of urban blocks in the Tokyo Metropolitan Region: estimation by urban block density and road width on the basis of normative plane tessellation. Int. J. Geogr. Inf. Sci. 32(1): 120-139 (2018) - [j4]Hiroyuki Usui:
Statistical distribution of building lot frontage: application for Tokyo downtown districts. J. Geogr. Syst. 20(3): 295-316 (2018) - [j3]Hiroyuki Usui:
Estimation of geometric route distance from its topological distance: application to narrow road networks in Tokyo. J. Geogr. Syst. 20(4): 387-412 (2018) - 2016
- [j2]Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, Onur Mutlu:
DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators. ACM Trans. Archit. Code Optim. 12(4): 65:1-65:28 (2016) - 2015
- [i1]Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, Onur Mutlu:
SQUASH: Simple QoS-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators. CoRR abs/1505.07502 (2015) - 2014
- [j1]Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe:
Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters. IEICE Trans. Electron. 97-C(4): 360-368 (2014) - [c5]Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori:
An evaluation of an energy efficient many-core SoC with parallelized face detection. ASP-DAC 2014: 311-316 - 2013
- [c4]Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe:
Development of low power many-core SoC for multimedia applications. DATE 2013: 773-777 - [c3]Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto:
A near-future prediction method for low power consumption on a many-core processor. DATE 2013: 1058-1059 - 2012
- [c2]Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori:
A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. VLSIC 2012: 150-151
2000 – 2009
- 2008
- [c1]Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi:
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. ISSCC 2008: 262-263
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