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ORCIDJ. Kelly Flanagan
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2000 – 2009
- 2005
[c18]Hyrum Carroll, J. Kelly Flanagan, Satish Baniya:
A Trace-Driven Simulator For Palm OS Devices. ISPASS 2005: 157-166- 2002
- [c17]Myles Watson, J. Kelly Flanagan:
Simulating L3 Caches in Real Time Using Hardware Accelerated Cache Simulation (HACS): A Case Study with SPECint 2000. SBAC-PAD 2002: 108-116 - 2001
- [j5]Niki C. Thornock, J. Kelly Flanagan:
A national trace collection and distribution resource. SIGARCH Comput. Archit. News 29(3): 6-10 (2001) - 2000
- [c16]Jeff Penfold, J. Kelly Flanagan:
A first year computer organization course on the web: make the magic disappear. WCAE 2000: 4 - [c15]Niki C. Thornock, J. Kelly Flanagan:
Facilitating level three cache studies using set sampling. WSC 2000: 471-479
1990 – 1999
- 1999
- [j4]Mark J. Clement, Glenn Judd, Bryan S. Morse, J. Kelly Flanagan:
Performance Surface Prediction for WAN-Based Clusters. J. Supercomput. 13(3): 267-281 (1999) - [c14]Franklin E. Sorenson, Elizabeth S. Sorenson, J. Kelly Flanagan, Heng Zhou:
A System-Assisted Disk I/O Simulation Technique. MASCOTS 1999: 296-304 - 1998
- [j3]J. Kelly Flanagan, James K. Archibald, Jun Su:
Low-power memory hierarchies: an argument for second-level caches. Microprocess. Microsystems 21(5): 279-290 (1998) - [c13]Mark J. Clement, Glenn Judd, Joy L. Peterson, Bryan S. Morse, J. Kelly Flanagan:
Performance Surface Prediction for WAN-Based Clusters. HICSS (7) 1998: 564-573 - 1997
- [c12]Mark J. Clement, Bryan S. Morse, J. Kelly Flanagan, Wei Wei, Phyllis E. Crandall:
The Chordal Spoke ATM Interconnection Network. PDPTA 1997: 1259-1267 - [c11]Niki C. Thornock, Xiao-Hong Tu, J. Kelly Flanagan:
A Stochastic Disk I/O Simulation Technique. WSC 1997: 1079-1086 - 1996
- [j2]Charlton D. Rose, J. Kelly Flanagan:
Constructing instruction traces from cache-filtered address traces (CITCAT). SIGARCH Comput. Archit. News 24(5): 1-8 (1996) - [c10]J. Kelly Flanagan, Brent E. Nelson, James K. Archibald, Gregory D. Thompson:
The Inaccuracy of Trace-Driven Simulation Using Incomplete Mulitprogramming Trace Data. MASCOTS 1996: 37-43 - [c9]Brent E. Nelson, Gregory D. Thompson, J. Kelly Flanagan:
Transaction Processing Workloads - A Comparison to the SPEC Benchmarks Using Memory Hierarchy Performance Studies. MASCOTS 1996: 152-156 - [c8]Mark J. Clement, J. Kelly Flanagan, Michael R. Steed:
Cost Optimal Analysis for Workstation Clusters. PDPTA 1996: 1308-1318 - 1995
- [c7]Wei Wei, Mark J. Clement, J. Kelly Flanagan:
The Round Table ATM Interconnection Network. PDPTA 1995: 445-454 - 1993
- [j1]Knuth Stener Grimsrud, James K. Archibald, M. Ripley, J. Kelly Flanagan, Brent E. Nelson:
BACH: a hardware monitor for tracing microprocessor-based systems. Microprocess. Microsystems 17(8): 443-459 (1993) - [c6]J. Kelly Flanagan, Brent E. Nelson, James K. Archibald, Knuth Stener Grimsrud:
Incomplete Trace Data and Trace Driven Simulation. MASCOTS 1993: 203-209 - 1991
- [c5]Brent E. Nelson, James K. Archibald, J. Kelly Flanagan:
Performance analysis of inclusion effects in multi-level multiprocessor caches. SPDP 1991: 513-516
1980 – 1989
- 1989
- [c4]Christopher J. Read, Douglas M. Chabries, Richard W. Christiansen, J. Kelly Flanagan:
A method for computing the DFT of vector quantized data. ICASSP 1989: 1015-1018 - [c3]J. Kelly Flanagan, Darryl Morrell, Richard L. Frost, Christopher J. Read, Brent E. Nelson:
Vector quantization codebook generation using simulated annealing. ICASSP 1989: 1759-1762 - 1988
- [c2]J. Kelly Flanagan, Brent E. Nelson:
Processor design using path programmable logic. ICCD 1988: 196-199 - 1987
- [c1]Tao Li, Brent E. Nelson, J. Kelly Flanagan, Christopher J. Read:
A multiprogrammed parallel architecture for digital signal processing. ICASSP 1987: 1390-1393
Coauthor Index
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