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2020 – today
- 2024
[c17]Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros:
Alternate Path μ-op Cache Prefetching. ISCA 2024: 1230-1245- 2023
- [j6]Chandana S. Deshpande
, Arthur Perais, Frédéric Pétrot:
Toward Practical 128-Bit General Purpose Microarchitectures. IEEE Comput. Archit. Lett. 22(2): 81-84 (2023) - [c16]Josué Feliu, Arthur Perais, Daniel A. Jiménez, Alberto Ros:
Rebasing Microarchitectural Research with Industry Traces. IISWC 2023: 100-114 - [c15]Arthur Perais, Rami Sheikh:
Branch Target Buffer Organizations. MICRO 2023: 240-253 - 2022
- [c14]Ashkan Asgharzadeh, Juan M. Cebrian, Arthur Perais, Stefanos Kaxiras, Alberto Ros:
Free atomics: hardware atomic operations without fences. ISCA 2022: 14-26 - [c13]Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros:
Exploring Instruction Fusion Opportunities in General Purpose Processors. MICRO 2022: 199-212 - 2021
- [j5]Arthur Perais:
A Case for Speculative Strength Reduction. IEEE Comput. Archit. Lett. 20(1): 22-25 (2021) - [c12]Arthur Perais:
Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction Potential. MICRO 2021: 792-803 - 2020
- [c11]Moritz Lipp, Vedad Hadzic, Michael Schwarz, Arthur Perais, Clémentine Maurice, Daniel Gruss:
Take A Way: Exploring the Security Implications of AMD's Cache Way Predictors. AsiaCCS 2020: 813-825
2010 – 2019
- 2019
- [c10]Arthur Perais, Rami Sheikh, Luke Yen, Michael McIlvaine, Robert D. Clancy:
Elastic Instruction Fetching. HPCA 2019: 478-490 - 2018
- [c9]Arthur Perais, André Seznec:
Cost effective speculation with the omnipredictor. PACT 2018: 25:1-25:13 - [c8]Vignyan Reddy Kothinti Naresh, Rami Sheikh, Arthur Perais, Harold W. Cain:
SPF: Selective Pipeline Flush. ICCD 2018: 152-155 - 2017
- [j4]Arthur Perais, André Seznec:
Storage-Free Memory Dependency Prediction. IEEE Comput. Archit. Lett. 16(2): 149-152 (2017) - [j3]Fernando A. Endo, Arthur Perais, André Seznec:
On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE. ACM Trans. Archit. Code Optim. 14(2): 18:1-18:24 (2017) - 2016
- [j2]Arthur Perais, André Seznec:
EOLE: Combining Static and Dynamic Scheduling Through Value Prediction to Reduce Complexity and Increase Performance. ACM Trans. Comput. Syst. 34(2): 4:1-4:33 (2016) - [c7]Arthur Perais, André Seznec:
Cost effective physical register sharing. HPCA 2016: 694-706 - [c6]Arthur Perais, Fernando A. Endo, André Seznec:
Register sharing for equality prediction. MICRO 2016: 4:1-4:12 - 2015
- [b1]Arthur Perais:
Increasing the performance of superscalar processors through value prediction. (La prédiction de valeurs comme moyen d'augmenter la performance des processeurs superscalaires). University of Rennes 1, France, 2015 - [j1]Arthur Perais, André Seznec:
EOLE: Toward a Practical Implementation of Value Prediction. IEEE Micro 35(3): 114-124 (2015) - [c5]Arthur Perais, André Seznec:
BeBoP: A cost effective predictor infrastructure for superscalar value prediction. HPCA 2015: 13-25 - [c4]Arthur Perais, André Seznec, Pierre Michaud, Andreas Sembrant, Erik Hagersten:
Cost-effective speculative scheduling in high performance processors. ISCA 2015: 247-259 - [c3]Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer, Arthur Perais, André Seznec, Pierre Michaud:
Long term parking (LTP): criticality-aware resource allocation in OOO processors. MICRO 2015: 334-346 - 2014
- [c2]Arthur Perais, André Seznec:
Practical data value speculation for future high-end processors. HPCA 2014: 428-439 - [c1]Arthur Perais, André Seznec:
EOLE: Paving the way for an effective implementation of value prediction. ISCA 2014: 481-492
Coauthor Index
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