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ORCIDFrancois Atallah
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2010 – 2019
- 2019
[c8]Francois Atallah, Keith A. Bowman
, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Yu Sun, Brad Appel, Anthony Polomik, Mahesh Harinath, Joshua Morelli, Thomas Moore, Nathaniel Reeves, Amer Cassier, Arijit Raychowdhury:
A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. ISSCC 2019: 316-318- [c7]Keith A. Bowman, Samantak Gangopadhyay, Francois Atallah, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Anthony Polomik, Mahesh Harinath, Nathaniel Reeves, Amer Cassier, Brad Appel, Arijit Raychowdhury:
A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. VLSI Circuits 2019: 126- - 2018
- [c6]Hoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman:
A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory. VLSI Circuits 2018: 1-2 - 2017
- [c5]Samantak Gangopadhyay, Saad Bin Nasir, Hoan Nguyen, Jihoon Jeong, Francois Atallah, Keith A. Bowman, Arijit Raychowdhury:
Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. CICC 2017: 1-4 - 2016
- [j2]Alexander E. Shapiro, Francois Atallah, Kyugseok Kim, Jihoon Jeong, Jeff Fischer, Eby G. Friedman:
Adaptive power gating of 32-bit Kogge Stone adder. Integr. 53: 80-87 (2016) - [j1]Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. IEEE J. Solid State Circuits 51(1): 8-17 (2016) - 2015
- [c4]Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine:
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. CICC 2015: 1-4 - [c3]Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. ISSCC 2015: 1-3 - 2014
- [c2]Alex Park, Venkat Narayanan, Keith A. Bowman, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine:
Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors. CICC 2014: 1-4 - [c1]Keith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine:
Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors. ITC 2014: 1
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