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2020 – today
- 2024
[j20]Jing Mai
, Jiarui Wang, Zhixiong Di, Yibo Lin:
Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 641-653 (2024)- [j19]Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin:
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1259-1272 (2024) - [j18]Zhengguang Tang, Cong Li, Hailong You, Zhixiong Di, Linying Zhang, Xingming Liu, Yu Wang, Yong Dai, Geng Bai:
Semi-Supervised Transfer Learning Framework for Aging-Aware Library Characterization. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1156-1160 (2024) - [j17]Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin:
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2034-2038 (2024) - [c7]Zhixiong Di, Xufeng Wei, Yiduo Chen, Shuanglong Wu, Peihao Sun, Qiang Wu:
A Remote FPGA-based Experimental Teaching System Design Supporting Single-board Multi-user and Multi-board Single-user Operations in MOOCs. ACM Great Lakes Symposium on VLSI 2024: 742-747 - 2023
- [j16]Weitao Pan, Meng Dong, Cong Wen, Hongjin Liu, Shaolin Zhang, Bo Shi, Zhixiong Di, Zhiliang Qiu, Yiming Gao, Ling Zheng:
A unioned graph neural network based hardware Trojan node detection. IEICE Electron. Express 20(13): 20230204 (2023) - [j15]Qiang Wu, Linjun Wu, Yongyuan Li, Xun Li, Zhixiong Di, Shubin Liu, Zhangming Zhu:
A High Precision CV Control Scheme for Low Power AC-DC BUCK Converter Controller. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 4183-4193 (2023) - [c6]Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin:
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. ASICON 2023: 1-4 - [c5]Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin:
A Robust FPGA Router with Concurrent Intra-CLB Rerouting. ASP-DAC 2023: 529-534 - [i5]Jing Mai, Jiarui Wang, Zhixiong Di, Yibo Lin:
Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. CoRR abs/2303.09305 (2023) - [i4]Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin:
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. CoRR abs/2306.16665 (2023) - [i3]Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin:
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction. CoRR abs/2308.03231 (2023) - [i2]Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin:
LEAPS: Topological-Layout-Adaptable Multi-die FPGA Placement for Super Long Line Minimization. CoRR abs/2308.03233 (2023) - 2022
- [j14]Zhixiong Di, Xuan Chen, Qiang Wu, Jiangyi Shi, Quanyuan Feng, Yibo Fan:
Learned Compression Framework With Pyramidal Features and Quality Enhancement for SAR Images. IEEE Geosci. Remote. Sens. Lett. 19: 1-5 (2022) - [j13]Qihan Xu, Yunfan Xiang, Zhixiong Di, Yibo Fan, Quanyuan Feng, Qiang Wu, Jiangyi Shi:
Synthetic Aperture Radar Image Compression Based on a Variational Autoencoder. IEEE Geosci. Remote. Sens. Lett. 19: 1-5 (2022) - [j12]Jinwei Chen, Zhixiong Di, Jiangyi Shi, Quanyuan Feng, Qiang Wu:
NBLG: A Robust Legalizer for Mixed-Cell-Height Modern Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4681-4693 (2022) - [j11]Zhenyu Shao, Zhixiong Di, Quanyuan Feng, Qiang Wu, Yibo Fan, Xulin Yu, Wenqiang Wang:
A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 209-213 (2022) - [j10]Xuan Chen, Zhixiong Di, Wei Wu, Qiang Wu, Jiangyi Shi, Quanyuan Feng:
Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning Model. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 564-568 (2022) - [j9]Qiang Wu, Xun Li, Yongyuan Li, Zhixiong Di, Quanyuan Feng:
Implementation of High Precision Error Amplification Scheme for AC-DC Converter. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1522-1526 (2022) - [j8]Xiao Yan, Zhixiong Di, Bowen Huang, Minjiang Li, Wenqiang Wang, Xiaoyang Zeng, Yibo Fan:
A High Throughput and Energy Efficient Lepton Hardware Encoder With Hash-Based Memory Optimization. IEEE Trans. Circuits Syst. Video Technol. 32(7): 4680-4695 (2022) - [j7]Qiang Wu, Xun Li, Yueyun Han, Zhixiong Di, Quanyuan Feng:
A Valley-Locking Control Scheme for an Audible Noise-Free Valley-Skip-Mode Flyback Converter. IEEE Trans. Ind. Electron. 69(7): 7285-7294 (2022) - [c4]Jing Mai, Yibai Meng, Zhixiong Di, Yibo Lin:
Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility. DAC 2022: 649-654 - 2021
- [c3]Zhixiong Di, Yongming Tang, Jiahua Lu, Zhaoyang Lv:
ASIC Design Principle Course with Combination of Online-MOOC and Offline-Inexpensive FPGA Board. ACM Great Lakes Symposium on VLSI 2021: 431-436 - [i1]Xiao Yan, Zhixiong Di, Bowen Huang, Minjiang Li, Wenqiang Wang, Xiaoyang Zeng, Yibo Fan:
A Power and Area Efficient Lepton Hardware Encoder with Hash-based Memory Optimization. CoRR abs/2105.01415 (2021) - 2020
- [j6]Wei Wu, Zhixiong Di, Jiangyi Shi, Quanyuan Feng, Zhengguang Tang:
A local congestion elimination technique driven by overflow. IEICE Electron. Express 17(17): 20200232 (2020) - [j5]Jiangyi Shi, Bo Zhao, Zhengguang Tang, Peijun Ma, Zhixiong Di:
A self-clocked binary-seaching digital low-dropout regulator with fast transient response. IEICE Electron. Express 17(21): 20200297 (2020)
2010 – 2019
- 2019
- [j4]Yinghui Tian, Yong Hei, Zhizhe Liu, Qi Shen, Zhixiong Di, Tao Chen:
A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 106-110 (2019) - [c2]Lintao Li, Jiangyi Shi, Zhixiong Di:
High Parallel VLSI Architecture Design of BPC in JPEG2000. ASICON 2019: 1-4 - 2017
- [j3]Yinghui Tian, Yong Hei, Zhizhe Liu, Zhixiong Di, Qi Shen, Zenghui Yu:
A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes. IEICE Electron. Express 14(15): 20170660 (2017) - [j2]Yinghui Tian, Yong Hei, Zhizhe Liu, Zhixiong Di, Qi Shen, Zenghui Yu:
Erratum: A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes [IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170660]. IEICE Electron. Express 14(22): 20178005 (2017) - 2015
- [j1]Zhixiong Di, Yue Hao, Jiangyi Shi, Peijun Ma:
A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000. J. Signal Process. Syst. 81(2): 227-247 (2015) - [c1]Zhixiong Di, Yanlong Wang, Shuang Qiao, Qianyin Xiang, Quanyuan Feng:
LC-KO: A congestion-aware and area&timing-oriented placement method. ASICON 2015: 1-4
Coauthor Index
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last updated on 2024-09-10 02:12 CEST by the dblp team
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