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ORCIDQingjun Fan
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- affiliation: University of Houston, Texas, USA
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2020 – today
- 2022
[j2]Yulang Feng
, Hao Deng, Qingjun Fan, Yuxuan Tang, Phaneendra Bikkina, Esko Mikkola, Jinghong Chen:
A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 625-633 (2022)- 2020
- [j1]Qingjun Fan, Yi Hong, Jinghong Chen:
A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive Calibration. IEEE J. Solid State Circuits 55(8): 2082-2093 (2020) - [c15]Yulang Feng, Hao Deng, Qingjun Fan, Runxi Zhang, Phaneendra Bikkina, Jinghong Chen:
A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI. ISCAS 2020: 1-4 - [c14]Runxi Zhang, Hui Yang, Zitong Zhang, Chunqi Shi, Qingjun Fan, Jinghong Chen:
A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications. ISCAS 2020: 1-4 - [c13]Yulang Feng, Qingjun Fan, Hao Deng, Jeffrey Chen, Runxi Zhang, Phaneendra Bikkina, Jinghong Chen:
An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology. LASCAS 2020: 1-4 - [c12]Hao Deng, Qingjun Fan, Runxi Zhang, Jinghong Chen:
Machine-Learning Based Nonlinerity Correction for Coarse-Fine SAR-TDC Hybrid ADC. MWSCAS 2020: 265-268
2010 – 2019
- 2019
- [c11]Qingjun Fan, Jinghong Chen:
A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology. ESSCIRC 2019: 99-102 - [c10]Qingjun Fan, Runxi Zhang, Phaneendra Bikkina, Esko Mikkola, Jinghong Chen:
A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator. ESSCIRC 2019: 193-196 - [c9]Qingjun Fan, Jinghong Chen:
A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration. ESSCIRC 2019: 301-304 - [c8]Qingjun Fan, Jinghong Chen:
A 500-MS/s 13-Bit SAR-Assisted Time-Interleaved Digital-Slope ADC. ISCAS 2019: 1-5 - [c7]Yuxuan Tang, Qingjun Fan, Yulang Feng, Hao Deng, Runxi Zhang, Jinghong Chen:
A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS. ISCAS 2019: 1-4 - 2018
- [c6]Yulang Feng, Yuxuan Tang, Qingjun Fan, Jinghong Chen:
A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS. APCCAS 2018: 30-33 - [c5]Yuxuan Tang, Yulang Feng, Qingjun Fan, Runxi Zhang, Jinghong Chen:
A Current Reuse Wideband LNA with Complementary Noise and Distortion Cancellation for Ultrasound Imaging Applications. APCCAS 2018: 171-174 - 2017
- [c4]Phaneendra Bikkina, Qingjun Fan, Wenlan Wu, Jinghong Chen, Esko Mikkola:
RFI mitigating receiver back-end for radiometers. IGARSS 2017: 1255-1258 - [c3]Zhiheng Zuo, Qingjun Fan, Jinghong Chen:
A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz. ISCAS 2017: 1-4 - [c2]Qingjun Fan, Jinghong Chen:
A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement. MWSCAS 2017: 583-586 - 2016
- [c1]Yuxuan Tang, Yulang Feng, Zhiheng Zuo, Qingjun Fan, Cheng Fang, Jun Zou, Jinghong Chen:
Wideband LNA with 1.9 dB noise figure in 0.18 µm CMOS for high frequency ultrasound imaging applications. NEWCAS 2016: 1-4
Coauthor Index
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