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ORCIDDaisuke Oku
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2020 – today
- 2022
[j3]Daisuke Oku
, Masashi Tawada, Shu Tanaka, Nozomu Togawa:
How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins. IEEE Trans. Computers 71(1): 223-234 (2022)
2010 – 2019
- 2019
- [j2]Daisuke Oku, Kotaro Terada, Masato Hayashi, Masanao Yamaoka, Shu Tanaka, Nozomu Togawa:
A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines. IEICE Trans. Inf. Syst. 102-D(9): 1696-1706 (2019) - [c5]Kota Takehara, Daisuke Oku, Yoshiki Matsuda, Shu Tanaka, Nozomu Togawa:
A Multiple Coefficients Trial Method to Solve Combinatorial Optimization Problems for Simulated-annealing-based Ising Machines. ICCE-Berlin 2019: 64-69 - [c4]Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE 2019: 1-6 - 2018
- [j1]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018) - [c3]Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa:
An Ising model mapping to solve rectangle packing problem. VLSI-DAT 2018: 1-4 - 2017
- [c2]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
A robust scan-based side-channel attack method against HMAC-SHA-256 circuits. ICCE-Berlin 2017: 79-84 - 2016
- [c1]Daisuke Oku, Masao Yanagisawa, Nozomu Togawa:
Implementation evaluation of scan-based attack against a Trivium cipher circuit. APCCAS 2016: 220-223
Coauthor Index
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