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ORCIDMohamed Megahed
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2020 – today
- 2024
[j6]Mohamed Megahed
, Yusang Chun, Zhiping Wang, Tejasvi Anand:
An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation. IEEE J. Solid State Circuits 59(8): 2492-2505 (2024)- 2023
- [j5]Ahmed M. Elshewey, Mahmoud Y. Shams, Zahraa Tarek, Mohamed Megahed, El-Sayed M. El-Kenawy, Mohamed A. El-dosuky:
Weight Prediction Using the Hybrid Stacked-LSTM Food Selection Model. Comput. Syst. Sci. Eng. 46(1): 765-781 (2023) - [j4]Mohamed Megahed, Tejasvi Anand:
A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS. IEEE J. Solid State Circuits 58(5): 1386-1399 (2023) - 2022
- [j3]Yusang Chun, Mohamed Megahed, Ashwin Ramachandran, Tejasvi Anand:
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. IEEE J. Solid State Circuits 57(5): 1527-1541 (2022) - [c6]Xiaohui Lin, Mohamed Megahed, Tejasvi Anand:
A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. VLSI Technology and Circuits 2022: 188-189 - 2021
- [c5]Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand:
A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8. VLSI Circuits 2021: 1-2 - [c4]Zhiping Wang, Mohamed Megahed, Yusang Chun, Tejasvi Anand:
A Machine Learning Inspired Transceiver with ISI-Resilient Data Encoding: Hybrid-Ternary Coding + 2-Tap FFE + CTLE + Feature Extraction and Classification for 44.7dB Channel Loss in 7.3pJ/bit. VLSI Circuits 2021: 1-2 - 2020
- [j2]Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand:
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS. IEEE J. Solid State Circuits 55(7): 1946-1959 (2020)
2010 – 2019
- 2019
- [j1]Abhishekh Devaraj, Mohamed Megahed, Yutao Liu, Ashwin Ramachandran, Tejasvi Anand:
A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4876-4887 (2019) - [c3]Mohamed Megahed, Y. Ramadass, Tejasvi Anand:
A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm. CICC 2019: 1-4 - 2017
- [c2]Meike Zehlike, Francesco Bonchi, Carlos Castillo, Sara Hajian, Mohamed Megahed, Ricardo Baeza-Yates:
FA*IR: A Fair Top-k Ranking Algorithm. CIKM 2017: 1569-1578 - [i1]Meike Zehlike, Francesco Bonchi, Carlos Castillo, Sara Hajian, Mohamed Megahed, Ricardo Baeza-Yates:
FA*IR: A Fair Top-k Ranking Algorithm. CoRR abs/1706.06368 (2017) - 2016
- [c1]Mohamed Megahed, Mohamed R. M. Rizk, Sameh A. Ibrahim, Mohamed Dessouky:
12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications. ICECS 2016: 101-104
Coauthor Index
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