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ORCIDGary D. Hachtel
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- affiliation: University of Colorado, Boulder, CO, USA
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2000 – 2009
- 2006
[b4]Gary D. Hachtel, Fabio Somenzi:
Logic synthesis and verification algorithms. Springer 2006, ISBN 978-0-387-31004-6, pp. I-XXIII, 1-564- [b3]Chao Wang, Gary D. Hachtel, Fabio Somenzi:
Abstraction Refinement for Large Scale Model Checking. Series on Integrated Circuits and Systems, Springer 2006, ISBN 978-0-387-34155-2, pp. 1-179 - [j20]Chao Wang, Roderick Bloem
, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi:
Compositional SCC Analysis for Language Emptiness. Formal Methods Syst. Des. 28(1): 5-36 (2006) - [j19]Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi:
Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2297-2316 (2006) - 2004
- [c47]Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi:
Refining the SAT decision ordering for bounded model checking. DAC 2004: 535-538 - [c46]Chao Wang, Gary D. Hachtel, Fabio Somenzi:
Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking. ICCD 2004: 112-118 - 2003
- [c45]Chao Wang, Gary D. Hachtel, Fabio Somenzi:
The Compositional Far Side of Image Computation. ICCAD 2003: 334-341 - [c44]Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi:
Improving Ariadneýs Bundle by Following Multiple Threads in Abstraction Refinement. ICCAD 2003: 408-415 - 2002
- [c43]Chao Wang, Gary D. Hachtel:
Sharp Disjunctive Decomposition for Language Emptiness Checking. FMCAD 2002: 106-122 - 2001
- [c42]Chao Wang, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi:
Divide and Compose: SCC Refinement for Language Emptiness. CONCUR 2001: 456-471 - 2000
- [c41]Jae-Young Jang, In-Ho Moon, Gary D. Hachtel:
Iterative Abstraction-Based CTL Model Checking. DATE 2000: 502-507 - [c40]In-Ho Moon, Gary D. Hachtel, Fabio Somenzi:
Border-Block Triangular Form and Conjunction Schedule in Image Computation. FMCAD 2000: 73-90
1990 – 1999
- 1998
- [c39]Abelardo Pardo, Gary D. Hachtel:
Incremental CTL Model Checking Using BDD Subsetting. DAC 1998: 457-462 - [c38]In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley:
Approximate reachability don't cares for CTL model checking. ICCAD 1998: 351-358 - 1997
- [j18]R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Algebraic Decision Diagrams and Their Applications. Formal Methods Syst. Des. 10(2/3): 171-206 (1997) - [j17]Gary D. Hachtel, Fabio Somenzi:
A Symbolic Algorithms for Maximum Flow in 0-1 Networks. Formal Methods Syst. Des. 10(2/3): 207-219 (1997) - [j16]R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi:
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1101-1115 (1997) - [c37]Abelardo Pardo, Gary D. Hachtel:
Automatic Abstraction Techniques for Propositional µ-calculus Model Checking. CAV 1997: 12-23 - 1996
- [b2]Gary D. Hachtel, Fabio Somenzi:
Logic synthesis and verification algorithms. Kluwer 1996, ISBN 978-0-7923-9746-5, pp. I-XXIX, 1-564 - [j15]Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
Automatic state space decomposition for approximate FSM traversal based on circuit analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1451-1464 (1996) - [j14]Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi:
Algorithms for approximate FSM traversal based on state space decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1465-1478 (1996) - [j13]Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Markovian analysis of large finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1479-1493 (1996) - [c36]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS: A System for Verification and Synthesis. CAV 1996: 428-432 - [c35]Kavita Ravi, Abelardo Pardo, Gary D. Hachtel, Fabio Somenzi:
Modular Verification of Multipliers. FMCAD 1996: 49-63 - [c34]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS. FMCAD 1996: 248-256 - [c33]Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi:
Tearing based automatic abstraction for CTL model checking. ICCAD 1996: 76-81 - [c32]R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi:
Symbolic computation of logic implications for technology-dependent low-power synthesis. ISLPED 1996: 163-168 - 1995
- [c31]Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino:
Computing the Maximum Power Cycles of a Sequential Circuit. DAC 1995: 23-28 - [c30]Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi:
CMOS dynamic power estimation based on collapsible current source transistor modeling. ISLPD 1995: 111-116 - 1994
- [j12]Bernard Plessier, Gary D. Hachtel, Fabio Somenzi:
Extended BDDs: Trading off Canonicity for Structure in Verification Algorithms. Formal Methods Syst. Des. 4(2): 167-185 (1994) - [j11]June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi, Reily M. Jacoby:
Exact and heuristic algorithms for the minimization of incompletely specified state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 167-177 (1994) - [j10]Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel:
Exact calculation of synchronizing sequences based on binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8): 1024-1034 (1994) - [c29]Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Probabilistic Analysis of Large Finite State Machines. DAC 1994: 270-275 - [c28]Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
A State Space Decomposition Algorithm for Approximate FSM Traversal. EDAC-ETC-EUROASIC 1994: 137-141 - [c27]Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine. EDAC-ETC-EUROASIC 1994: 214-218 - [c26]R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi:
Timing Analysis of Combinational Circuits using ADD's. EDAC-ETC-EUROASIC 1994: 625-629 - [c25]R. Iris Bahar, Gary D. Hachtel, Abelardo Pardo, Massimo Poncino, Fabio Somenzi:
An ADD-based algorithm for shortest path back-tracing of large graphs. Great Lakes Symposium on VLSI 1994: 248-251 - [c24]Gary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi:
Re-encoding sequential circuits to reduce power dissipation. ICCAD 1994: 70-73 - [c23]R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi:
A symbolic method to reduce power consumption of circuits containing false paths. ICCAD 1994: 368-371 - [c22]Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. ICCD 1994: 236-239 - 1993
- [j9]Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi:
Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 935-945 (1993) - [c21]Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi:
Algorithms for Approximate FSM Traversal. DAC 1993: 25-30 - [c20]R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi:
Algebraic decision diagrams and their applications. ICCAD 1993: 188-191 - [c19]Gary D. Hachtel, Fabio Somenzi:
A symbolic algorithm for maximum flow in 0-1 networks. ICCAD 1993: 403-406 - 1992
- [j8]Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison:
On properties of algebraic transformations and the synthesis of multifault-irredundant circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3): 313-321 (1992) - [c18]Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel:
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. DAC 1992: 620-623 - 1991
- [j7]Xuejun Du, Gary D. Hachtel, Bill Lin, A. Richard Newton:
MUSE: a multilevel symbolic encoding algorithm for state assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1): 28-38 (1991) - [c17]Gary D. Hachtel, June-Kyung Rho, Fabio Somenzi, Reily M. Jacoby:
Exact and heuristic algorithms for the minimization of incompletely specified state machines. EURO-DAC 1991: 184-191 - [c16]June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi:
Don't Care Sequences and the Optimization of Interacting Finite State Machines. ICCAD 1991: 418-421 - [c15]Seh-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi:
Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms. ICCAD 1991: 464-467 - [c14]Seon-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi:
Variable Ordering and Selection for FSM Traversal. ICCAD 1991: 476-479 - [c13]Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi:
Redundancy Identification and Removal Based on Implicit State Enumeration. ICCD 1991: 77-80 - [c12]Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi:
Fast Sequential ATPG Based on Implicit State Enumeration. ITC 1991: 67-74 - 1990
- [j6]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli:
Multilevel logic synthesis. Proc. IEEE 78(2): 264-300 (1990) - [c11]Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi:
Results on the Interface between Formal Verification and ATPG. CAV (DIMACS/AMS volume) 1990: 615-628 - [c10]Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi:
ATPG Aspects of FSM Verification. ICCAD 1990: 134-137
1980 – 1989
- 1989
- [j5]Gary D. Hachtel, Christopher R. Morrison:
Linear complexity algorithms for hierarchical routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(1): 64-80 (1989) - [c9]Glenn Colón-Bonet, Eric M. Schwarz, D. G. Bostick, Gary D. Hachtel, Michael R. Lightner:
On optimal extraction of combinational logic and don't care sets from hardware description languages. ICCAD 1989: 308-311 - [c8]Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison:
On properties of algebraic transformation and the multifault testability of multilevel logic. ICCAD 1989: 422-425 - [c7]Reily M. Jacoby, P. Moceyunas, Hyunwoo Cho, Gary D. Hachtel:
New ATPG techniques for logic optimization. ICCAD 1989: 548-551 - 1988
- [j4]Gary D. Hachtel, Reily M. Jacoby:
Verification algorithms for VLSI synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(5): 616-640 (1988) - [j3]Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
Multi-level logic minimization using implicit don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 723-740 (1988) - [c6]Hyunwoo Cho, Gary D. Hachtel, M. Nash, L. Setiono:
BEATNP: a tool for partitioning Boolean networks. ICCAD 1988: 10-13 - [c5]Gary D. Hachtel, Reily M. Jacoby, P. Moceyunas, Christopher R. Morrison:
Performance enhancements in BOLD using 'implications'. ICCAD 1988: 94-97 - 1986
- [j2]Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel:
Synthesis and Optimization of Multilevel Logic under Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 582-596 (1986) - [c4]David Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel:
SOCRATES: a system for automatically synthesizing and optimizing combinational logic. DAC 1986: 79-85 - 1984
- [b1]Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli:
Logic Minimization Algorithms for VLSI Synthesis. The Kluwer International Series in Engineering and Computer Science 2, Springer 1984, ISBN 978-1-4612-9784-0, pp. 1-193 - [c3]Michael R. Lightner, Gary D. Hachtel, Richard H. Byrd, Michel Heydemann:
A Theory and Algorithmic Frame for Switch Level Simulation. IMACS European Simulation Meeting 1984: 151-159 - 1982
- [j1]Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
An Algorithm for Optimal PLA Folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1(2): 63-77 (1982) - [c2]Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Techniques for programmable logic array folding. DAC 1982: 147-155 - [c1]Michael R. Lightner, Gary D. Hachtel:
Implication algorithms for MOS switch level functional macromodeling implication and testing. DAC 1982: 691-698
Coauthor Index
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