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2020 – today
- 2025
[j3]Disi Lin, Chuandong Chen, Rongshan Wei, Qinghai Liu, Huan He, Ziran Zhu, Zhifeng Lin
, Jianli Chen:
Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB. Integr. 100: 102270 (2025)- 2023
- [c3]Chuandong Chen, Dishi Lin, Rongshan Wei, Qinghai Liu, Ziran Zhu, Jianli Chen:
Efficient Global Optimization for Large Scaled Ordered Escape Routing. ASP-DAC 2023: 535-540 - [c2]Qinghai Liu, Disi Lin, Chuandong Chen, Huan He, Jianli Chen, Yao-Wen Chang:
A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints. DAC 2023: 1-6 - [c1]Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang:
Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints. DAC 2023: 1-6
2010 – 2019
- 2019
- [j2]Wei Hu, Haibo Luo, Chuandong Chen, Rongshan Wei:
A Multi-Interval Homotopy Analysis Method Using Multi-Objective Optimization for Analytically Analyzing Chaotic Dynamics in Memristive Circuit. IEEE Access 7: 116328-116341 (2019) - 2018
- [j1]Chuandong Chen, Rongshan Wei, Shaohao Wang, Wei Hu:
Novel Verification Method for Timing Optimization Based on DPSO. VLSI Design 2018: 8258397:1-8258397:8 (2018)
Coauthor Index
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