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ORCIDK. Wayne Current
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2000 – 2009
- 2008
[j15]Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(10): 3038-3049 (2008)- 2007
- [j14]K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews:
A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System. IEEE Trans. Biomed. Circuits Syst. 1(2): 105-115 (2007) - 2005
- [c24]K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews:
A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor. ICMENS 2005: 153-158 - [c23]Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS 2005: 724-732 - 2004
- [j13]Yongjian Brandon Guo, K. Wayne Current:
Low-Power Voltage Comparator Circuit for CMOS Quaternary Logic. J. Multiple Valued Log. Soft Comput. 10(3): 225-260 (2004) - 2002
- [c22]Yongjian Brandon Guo, K. Wayne Current:
Voltage Comparator Circuits for Multiple-Valued CMOS Logic. ISMVL 2002: 67-75 - 2000
- [j12]Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic
, K. Wayne Current:
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 460-463 (2000) - [c21]Dan Olson, K. Wayne Current:
Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts. ISMVL 2000: 371-376 - [c20]K. Wayne Current:
Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. ISMVL 2000: 377-381 - [c19]Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija:
Partitioned Branch Condition Resolution Logic. SBCCI 2000: 35-40
1990 – 1999
- 1998
- [c18]Jelena Popovic, Borivoje Nikolic, K. Wayne Current, Aleksandra Pavasovic, Dragan Vasiljevic:
CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyor. ICECS 1998: 349-352 - 1997
- [c17]Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current:
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. ISLPED 1997: 323-327 - 1996
- [c16]K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic:
Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. ISMVL 1996: 86-91 - 1995
- [j11]James F. Parker, K. Wayne Current, Stephen H. Lewis:
A CMOS continuous-time NTSC-to-color-difference decoder. IEEE J. Solid State Circuits 30(12): 1524-1532 (1995) - [c15]K. Wayne Current:
Memory Circuits for Multiple-Valued Logic Voltage Signals. ISMVL 1995: 52-57 - 1994
- [j10]K. Wayne Current:
Current-mode CMOS multiple-valued logic circuits. IEEE J. Solid State Circuits 29(2): 95-107 (1994) - [c14]Wei-Shang Chu, K. Wayne Current:
Quaternary Multiplier Circuit. ISMVL 1994: 15-18 - 1993
- [c13]K. Wayne Current, James F. Parker, Wes Hardaker:
Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs. ISCAS 1993: 2090-2093 - [c12]K. Wayne Current:
Multiple Valued Logic: Current-Mode CMOS Circuits. ISMVL 1993: 176-181 - 1992
- [j9]Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi:
High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture. IEEE Trans. Circuits Syst. Video Technol. 2(4): 347-360 (1992) - [c11]K. Wayne Current:
A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit. ISMVL 1992: 229-234 - 1991
- [c10]J. Liu, Ziqiang Mao, G. Z. Lu, W. H. Han, Tien C. Hsia, K. Wayne Current, Wei-Shang Chu:
A new VLSI architecture for real-time control of robot manipulators. ICRA 1991: 1828-1835 - [c9]K. Wayne Current, M. E. Hurlston:
A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit. ISMVL 1991: 196-202 - 1990
- [j8]K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi:
An evaluation of Radon transform computations using DSP chips. Mach. Vis. Appl. 3(2): 63-74 (1990) - [c8]Paul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh:
A VLSI architecture for two-dimensional Radon transform computations. ICASSP 1990: 933-936 - [c7]K. Wayne Current:
A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. ISMVL 1990: 168-173
1980 – 1989
- 1989
- [j7]James M. Apffel, K. Wayne Current, Jorge L. C. Sanz, Anil K. Jain:
An architecture for region boundary extraction in raster scan images suitable for VLSI implementation. Mach. Vis. Appl. 2(4): 193-214 (1989) - [c6]Stephen G. Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain, K. Wayne Current, Paul J. Hurst:
A Radon transform computer for multidimensional signal processing. ICASSP 1989: 1457-1459 - 1988
- [c5]J. R. Parkhurst, K. Wayne Current, Anil K. Jain, J. E. Grishaw:
A unified DCT/IDCT architecture for VLSI implementation. ICASSP 1988: 1993-1996 - 1986
- [j6]James L. Mangin, K. Wayne Current:
Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits. IEEE Trans. Computers 35(2): 157-161 (1986) - 1985
- [j5]Stephen B. Haley, K. Wayne Current:
Response change in linearized circuits and systems: Computational algorithms and applications. Proc. IEEE 73(1): 5-24 (1985) - 1980
- [j4]K. Wayne Current:
High Density Integrated Computing Circuitry with Multiple Valued Logic. IEEE Trans. Computers 29(2): 191-195 (1980) - [j3]K. Wayne Current:
Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. IEEE Trans. Computers 29(5): 400-403 (1980) - [j2]K. Wayne Current:
A High Data-Rate Digital Output Correlator Design. IEEE Trans. Computers 29(5): 403-405 (1980)
1970 – 1979
- 1979
- [j1]K. Wayne Current, Douglas A. Mow:
Implementing Parallel Counters with Four-Valued Threshold Logic. IEEE Trans. Computers 28(3): 200-204 (1979) - [c4]K. Wayne Current, Douglas A. Mow, S. Youssef-Digaleh:
A high data rate, low power all-digital correlation circuit design. ICASSP 1979: 859-862 - 1978
- [c3]K. Wayne Current, Douglas A. Mow:
Parallel counter design using four-valued threshold logic. ICASSP 1978: 796-799 - [c2]K. Wayne Current, Douglas A. Mow:
Four-valued threshold logic full adder circuit implementations. MVL 1978: 95-100 - [c1]K. Wayne Current, Douglas A. Mow:
Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits. MVL 1978: 187
Coauthor Index
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