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2020 – today
- 2023
[j2]Xianwu Hu
, Yu Wang, Zizhao Ma, Gan Wen, Zeming Wang, Zhichao Lu, Yunlong Liu, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4216-4220 (2023)- [c6]Zizhao Ma, Xianwu Hu, Gan Wen, Yihao Wang, Zeming Wang, Yukai Lin, Yu Wang, Yuhao Guo, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications. A-SSCC 2023: 1-3 - [c5]Zizhao Ma, Xianwu Hu, Yihao Wang, Gan Wen, Xiaoyang Zeng, Yufeng Xie:
A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation. ISCAS 2023: 1-5 - 2022
- [c4]Xianwu Hu, Yu Wang, Jiayun Feng, Zizhao Ma, Xiaoyang Zeng, Yufeng Xie:
A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process. ISCAS 2022: 2438-2442 - 2021
- [c3]Xianwu Hu, Dongyang Li, Yu Wang, Jiayun Feng, Zizhao Ma, Shaohao Wang, Tai Min, Xiaoyang Zeng, Yufeng Xie:
An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process. ASICON 2021: 1-4 - [c2]Yukai Lin, Yu Wang, Xianwu Hu, Jiayun Feng, Gan Wen, Xiankui Xiong, Haidong Tian, Yufeng Xie:
A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight. ASICON 2021: 1-4
2010 – 2019
- 2019
- [c1]Danqing Wu, Shilin Yan, Haodi Tang, Yu Wang, Jiayun Feng, Xianwu Hu, Jiaxin Cao, Yufeng Xie:
A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme. ASICON 2019: 1-4 - 2012
- [j1]Xianwu Hu:
The Establishment of Supply Chain with Game Model of Competition and Cooperation. J. Softw. 7(3): 670-677 (2012)
Coauthor Index
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