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ORCIDMuhammed Bolatkale
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2020 – today
- 2024
[j6]Sundeep Javvaji
, Muhammed Bolatkale, Shagun Bajoria, Robert Rutten, Bert Oude-Essink, Koen Beijens, Kofi A. A. Makinwa, Lucien J. Breems:
A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme. IEEE J. Solid State Circuits 59(4): 1184-1193 (2024)- 2023
- [c17]Sundeep Javvaji, Muhammed Bolatkale, Shagun Bajoria, Robert Rutten, Bert Oude-Essink, Koen Beijens, Kofi A. A. Makinwa, Lucien J. Breems:
A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j5]Muhammed Bolatkale, Robert Rutten, Hans Brekelmans, Shagun Bajoria, Yihan Gao, Bernard Burdiek, Lucien J. Breems:
A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction. IEEE J. Solid State Circuits 57(12): 3768-3780 (2022) - [j4]Qilong Liu, Lucien J. Breems, Shagun Bajoria, Muhammed Bolatkale, Robert Rutten, Georgi I. Radulov:
A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS. IEEE J. Solid State Circuits 57(12): 3781-3793 (2022) - [c16]Shubham Mehrotra, Efraïm Eland, Shoubhik Karmakar, Angqi Liu, Burak Gönen, Muhammed Bolatkale, Robert H. M. van Veldhoven, Kofi A. A. Makinwa:
A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC. ESSCIRC 2022: 253-256 - [c15]Pierluigi Cenci, Hans Brekelmans, Shagun Bajoria, Marcello Ganzerli, Bernard Burdiek, Robert Rutten, Yihan Gao, Muhammed Bolatkale, Paul Swinkels, Lucien J. Breems:
A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW. ESSCIRC 2022: 321-324 - [c14]Qilong Liu, Lucien J. Breems, Chenming Zhang, Shagun Bajoria, Muhammed Bolatkale, Robert Rutten, Georgi I. Radulov:
A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS. ISSCC 2022: 414-416 - [c13]Muhammed Bolatkale, Robert Rutten, Hans Brekelmans, Shagun Bajoria, Yihan Gao, Bernard Burdiek, Lucien J. Breems:
A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction. ISSCC 2022: 416-418 - 2021
- [c12]Chenming Zhang, Lucien J. Breems, Qilong Liu, Georgi I. Radulov, Muhammed Bolatkale, Shagun Bajoria, Robert Rutten, Arthur H. M. van Roermund:
A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS. ESSCIRC 2021: 491-494 - 2020
- [c11]Stijn Ringeling, Loek Steinebach, Qilong Liu, Chenming Zhang, Shagun Bajoria, Muhammed Bolatkale, Lucien J. Breems, Georgi I. Radulov:
Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators. ECCTD 2020: 1-4 - [c10]Qilong Liu, Lucien J. Breems, Shagun Bajoria, Muhammed Bolatkale, Chenming Zhang, Georgi I. Radulov:
Analysis of the Inter-Stage Signal Leakage in Wide BW Low OSR and High DR CT MASH ΔΣM. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c9]Pierluigi Cenci, Muhammed Bolatkale, Robert Rutten, M. Ganzerli, Gerard Lassche, Kofi A. A. Makinwa, Lucien J. Breems:
A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. VLSI Circuits 2019: 230- - 2018
- [c8]Marios Neofytou, Meiyi Zhou, Muhammed Bolatkale, Qilong Liu, Chenming Zhang, Georgi I. Radulov, Peter G. M. Baltus, Lucien J. Breems:
A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications. ISCAS 2018: 1-5 - [c7]Meiyi Zhou, Marios Neofytou, Muhammed Bolatkale, Qilong Liu, Chenming Zhang, Pierluigi Cenci, Georgi I. Radulov, Peter G. M. Baltus, Lucien J. Breems:
A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT ΣΔ Modulator. ISCAS 2018: 1-5 - 2017
- [c6]Pierluigi Cenci, Muhammed Bolatkale, Robert Rutten, Gerard Lassche, Kofi A. A. Makinwa, Lucien J. Breems:
A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator. ESSCIRC 2017: 171-174 - [c5]Chenming Zhang, Lucien J. Breems, Georgi I. Radulov, Muhammed Bolatkale, Qilong Liu, Hans Hegt, Arthur H. M. van Roermund:
Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs. ISCAS 2017: 1-4 - 2016
- [j3]Lucien J. Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassche:
A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth. IEEE J. Solid State Circuits 51(12): 2906-2916 (2016) - [c4]Chenming Zhang, Lucien J. Breems, Georgi I. Radulov, Muhammed Bolatkale, Hans Hegt, Arthur H. M. van Roermund:
A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements. ISCAS 2016: 1486-1489 - [c3]Lucien J. Breems, Muhammed Bolatkale, Hans Brekelmans, Shagun Bajoria, Jan Niehof, Robert Rutten, Bert Oude-Essink, Franco Fritschij, Jagdip Singh, Gerard Lassche:
15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW. ISSCC 2016: 272-273 - 2011
- [j2]Muhammed Bolatkale, Michiel A. P. Pertijs, Wilko J. Kindt, Johan H. Huijsing, Kofi A. A. Makinwa:
A Single-Temperature Trimming Technique for MOS-Input Operational Amplifiers Achieving 0.33 μ V/°C Offset Drift. IEEE J. Solid State Circuits 46(9): 2099-2107 (2011) - [j1]Muhammed Bolatkale, Lucien J. Breems, Robert Rutten, Kofi A. A. Makinwa:
A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW. IEEE J. Solid State Circuits 46(12): 2857-2868 (2011) - [c2]Muhammed Bolatkale, Lucien J. Breems, Robert Rutten, Kofi A. A. Makinwa:
A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW. ISSCC 2011: 470-472
2000 – 2009
- 2008
- [c1]Muhammed Bolatkale, Michiel A. P. Pertijs, Wilko J. Kindt, Johan H. Huijsing, Kofi A. A. Makinwa:
A BiCMOS Operational Amplifier Achieving 0.33μV°C Offset Drift using Room-Temperature Trimming. ISSCC 2008: 76-77
Coauthor Index
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