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Matthew Horsnell
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2020 – today
- 2023
- [c9]Steffen Jensen, Jaekyu Lee, Dam Sunwoo, Matt Horsnell, Matthew Siggs, Jeeho Ryoo, Lizy K. John:
Do Video Encoding Workloads Stress the Microarchitecture? IISWC 2023: 54-64 - 2022
- [c8]Steffen Jensen, Jaekyu Lee, Dam Sunwoo, Matthew J. Horsnell, Lizy K. John:
Microarchitectural Performance Evaluation of AV1 Video Encoding Workloads. ISPASS 2022: 251-253 - 2020
- [i3]Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian:
The gem5 Simulator: Version 20.0+. CoRR abs/2007.03152 (2020) - [i2]Kris Nikov, José L. Núñez-Yáñez, Matthew Horsnell:
Evaluation of hybrid run-time power models for the ARM big.LITTLE architecture. CoRR abs/2008.10604 (2020)
2010 – 2019
- 2018
- [i1]Nigel Stephens, Stuart Biles, Matthias Boettcher, Jacob Eapen, Mbou Eyole, Giacomo Gabrielli, Matt Horsnell, Grigorios Magklis, Alejandro Martinez, Nathanaël Prémillieu, Alastair Reid, Alejandro Rico, Paul Walker:
The ARM Scalable Vector Extension. CoRR abs/1803.06185 (2018) - 2017
- [j2]Nigel Stephens, Stuart Biles, Matthias Boettcher, Jacob Eapen, Mbou Eyole, Giacomo Gabrielli, Matt Horsnell, Grigorios Magklis, Alejandro Martinez, Nathanaël Prémillieu, Alastair Reid, Alejandro Rico, Paul Walker:
The ARM Scalable Vector Extension. IEEE Micro 37(2): 26-39 (2017) - 2015
- [c7]Krastin Nikov, José L. Núñez-Yáñez, Matthew Horsnell:
Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture. EUC 2015: 205-210 - 2010
- [c6]Behram Khan, Matthew Horsnell, Mikel Luján, Ian Watson:
Scalable Object-Aware Hardware Transactional Memory. Euro-Par (1) 2010: 268-279
2000 – 2009
- 2009
- [j1]Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, Ian Watson:
Exploiting object structure in hardware transactional memory. Comput. Syst. Sci. Eng. 24(5) (2009) - 2008
- [c5]Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, Ian Watson:
An Object-Aware Hardware Transactional Memory System. HPCC 2008: 93-102 - [c4]Jisheng Zhao, Matthew Horsnell, Mikel Luján, Ian Rogers, Chris C. Kirkham, Ian Watson:
Adaptive Loop Tiling for a Multi-cluster CMP. ICA3PP 2008: 220-232 - [c3]Konstantinos Nikas, Matthew Horsnell, Jim D. Garside:
An adaptive bloom filter cache partitioning scheme for multicore architectures. ICSAMOS 2008: 25-32 - [c2]Behram Khan, Matthew Horsnell, Ian Rogers, Mikel Luján, Andrew Dinn, Ian Watson:
A first insight into object-aware hardware transactional memory. SPAA 2008: 107-109 - 2007
- [c1]Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew Dinn, Chris C. Kirkham, Ian Watson:
Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation. Euro-Par 2007: 258-267
Coauthor Index
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