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ORCIDYasuo Itoh
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2010 – 2019
- 2014
[j10]Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka:
A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving. IEEE J. Solid State Circuits 49(11): 2526-2533 (2014)
2000 – 2009
- 2008
- [j9]Mayumi Oyama-Higa, Tiejun Miao, Yasuo Itoh:
Relationship between fractal dimension and favorability of facial imagery. Int. J. Hybrid Intell. Syst. 5(4): 169-178 (2008) - [c3]Yasuo Itoh, Mayumi Oyama-Higa, Tiejun Miao:
Is the perceived agreeability of a face related to the fractal dimension of the face? SMC 2008: 2960-2965 - 2007
- [c2]Yasuo Itoh, Mayumi Oyama:
Does the transition of the interval in perceptional alternation have a chaotic rhythm? SMC 2007: 3135-3139 - 2006
- [j8]Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada:
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. 89-C(3): 250-262 (2006) - 2001
- [j7]Daisaburo Takashima, Yoshiaki Takeuchi, Tadashi Miyakawa, Yasuo Itoh, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Sumiko Mano Doumae, Tohru Ozaki, Hiroyuki Kanaya, Koji Yamakawa, Iwao Kunishima, Yukihito Oowaki:
A 76-mm2 8-Mb chain ferroelectric memory. IEEE J. Solid State Circuits 36(11): 1713-1720 (2001) - 2000
- [j6]Ryu Ogiwara, Sumio Tanaka, Yasuo Itoh, Tadashi Miyakawa, Yoshiaki Takeuchi, Sumiko Mano Doumae, Hiroyuki Takenaka, Iwao Kunishima, Susumu Shuto, Osamu Hidaka, Sumito Ohtsuki, Shin'ichi Tanaka:
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. IEEE J. Solid State Circuits 35(4): 545-551 (2000)
1990 – 1999
- 1997
- [j5]Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto:
A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. IEEE J. Solid State Circuits 32(5): 670-680 (1997) - 1995
- [j4]Yoshihisa Iwata, Ken-ichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Hideko Oodaira, Masaki Momodomi, Yasuo Itoh, Toshiharu Watanabe, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Junichi Miyamoto:
A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. IEEE J. Solid State Circuits 30(11): 1157-1164 (1995)
1980 – 1989
- 1989
- [j3]Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka:
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. IEEE J. Solid State Circuits 24(3): 763-770 (1989) - [j2]Kenji Numata, Yukihito Oowaki, Yasuo Itoh, Takahiko Hara, Kenji Tsuchida, Masako Ohta, Shigyoshi Watanabe, Kazunori Ohuchi:
New nibbled-page architecture for high-density DRAMs. IEEE J. Solid State Circuits 24(4): 900-904 (1989) - [j1]Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka:
An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. IEEE J. Solid State Circuits 24(5): 1238-1243 (1989) - 1983
- [c1]Kazunori Ozawa, Takashi Araseki, Yasuo Itoh:
An adaptive echo canceller using digital signal processor LSI chips. ICASSP 1983: 466-469
Coauthor Index
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