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ORCIDAnshuman Chandra
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2020 – today
- 2024
[c29]Erik Jan Marinissen, Adrian Evans, Po-Yao Chuang, Martin Keim, Anshuman Chandra:
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405. ETS 2024: 1-10- 2023
- [c28]Anshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora:
A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation. ITC 2023: 11-20
2010 – 2019
- 2015
- [c27]Subramanian Chebiyam, Anshuman Chandra, Rohit Kapur:
Designing effective scan compression solutions for industrial circuits. ISQED 2015: 167-172 - [c26]Anshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur:
Designing efficient combinational compression architecture for testing industrial circuits. VDAT 2015: 1-6 - 2014
- [c25]Anshuman Chandra, Subramanian Chebiyam, Rohit Kapur:
A Case Study on Implementing Compressed DFT Architecture. ATS 2014: 336-341 - [c24]Swapnil Bahl, Shreyans Rungta, Shray Khullar, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath, Ajay Rajagopalan:
Unifying scan compression. DFT 2014: 191-196 - 2013
- [c23]Anshuman Chandra:
Special session 11B: Hot topic on-chip clocking - Industrial trends. VTS 2013: 1 - 2011
- [c22]Uzair Shah Syed, Krishnendu Chakrabarty
, Anshuman Chandra, Rohit Kapur:
3D-Scalable Adaptive Scan (3D-SAS). 3DIC 2011: 1-6 - [c21]Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur:
Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C). Asian Test Symposium 2011: 432-437
2000 – 2009
- 2009
- [c20]Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa:
Scalable Adaptive Scan (SAS). DATE 2009: 1476-1481 - [c19]Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur:
Proactive management of X's in scan chains for compression. ISQED 2009: 260-265 - 2008
- [c18]Anshuman Chandra, Rohit Kapur:
Not All Xs are Bad for Scan Compression. ATS 2008: 7-12 - [c17]Anshuman Chandra, Felix Ng, Rohit Kapur:
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. DATE 2008: 462-467 - [c16]Anshuman Chandra, Rohit Kapur:
Interval Based X-Masking for Scan Compression Architectures. ISQED 2008: 821-826 - [c15]Anshuman Chandra, Rohit Kapur:
Bounded Adjacent Fill for Low Capture Power Scan Testing. VTS 2008: 131-138 - 2007
- [j14]Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri:
DFT MAX and Power. J. Low Power Electron. 3(2): 199-205 (2007) - [j13]Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra:
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 531-540 (2007) - [c14]Anshuman Chandra, Haihua Yan, Rohit Kapur:
Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. VTS 2007: 84-92 - 2006
- [j12]Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra:
Response compaction for system-on-a-chip based on advanced convolutional codes. Sci. China Ser. F Inf. Sci. 49(2): 262-272 (2006) - [j11]Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra:
Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. IEEE Trans. Instrum. Meas. 55(2): 389-399 (2006) - 2005
- [j10]Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen:
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Trans. Inf. Syst. 88-D(9): 2126-2134 (2005) - [j9]Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. 20(2): 201-209 (2005) - [c13]Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra:
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. Asian Test Symposium 2005: 372-377 - 2004
- [j8]Anshuman Chandra, Krishnendu Chakrabarty:
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes. J. Electron. Test. 20(2): 199-212 (2004) - [c12]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium 2004: 8-13 - [c11]Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT 2004: 298-305 - 2003
- [j7]Anshuman Chandra, Krishnendu Chakrabarty:
Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes. IEEE Trans. Computers 52(8): 1076-1088 (2003) - [j6]Anshuman Chandra, Krishnendu Chakrabarty:
A unified approach to reduce SOC test data volume, scan power and testing time. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 352-363 (2003) - [c10]Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium 2003: 440-445 - [c9]Vikram Iyengar, Anshuman Chandra, Sharon Schweizer, Krishnendu Chakrabarty:
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. DATE 2003: 11188-11190 - [c8]Vikram Iyengar, Anshuman Chandra:
A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design. DFT 2003: 511-518 - 2002
- [b1]Krishnendu Chakrabarty, Vikram Iyengar, Anshuman Chandra:
Test Resource Partitioning for System-on-a-Chip. Frontiers in electronic testing 20, Kluwer / Springer 2002, ISBN 978-1-4020-7119-5, pp. I-XII, 1-232 - [j5]Anshuman Chandra, Krishnendu Chakrabarty:
Low-power scan testing and test data compression forsystem-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 597-604 (2002) - [j4]Anshuman Chandra, Krishnendu Chakrabarty:
Test data compression and decompression based on internal scanchains and Golomb coding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 715-722 (2002) - [c7]Anshuman Chandra, Krishnendu Chakrabarty:
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. DAC 2002: 673-678 - [c6]Anshuman Chandra, Krishnendu Chakrabarty:
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression. DATE 2002: 598-603 - [c5]Anshuman Chandra, Krishnendu Chakrabarty, Rafael A. Medina:
How Effective are Compression Codes for Reducing Test Data Volume? VTS 2002: 91-96 - 2001
- [j3]Anshuman Chandra, Krishnendu Chakrabarty:
Test Resource Partitioning for SOCs. IEEE Des. Test Comput. 18(5): 80-91 (2001) - [j2]Anshuman Chandra, Krishnendu Chakrabarty:
System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 355-368 (2001) - [j1]Anshuman Chandra, Krishnendu Chakrabarty, Mark C. Hansen:
Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters. VLSI Design 12(4): 475-486 (2001) - [c4]Anshuman Chandra, Krishnendu Chakrabarty:
Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip. DAC 2001: 166-169 - [c3]Anshuman Chandra, Krishnendu Chakrabarty:
Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding. DATE 2001: 145-149 - [c2]Anshuman Chandra, Krishnendu Chakrabarty:
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression. VTS 2001: 42-47 - 2000
- [c1]Anshuman Chandra, Krishnendu Chakrabarty:
Test Data Compression for System-on-a-Chip Using Golomb Codes. VTS 2000: 113-120
Coauthor Index
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