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2020 – today
- 2020
[j47]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey
, Kartikeya Mayaram, Terri S. Fiez:
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. IEEE J. Solid State Circuits 55(3): 706-718 (2020)
2010 – 2019
- 2019
- [j46]Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez:
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 347-351 (2019) - [j45]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez:
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2440-2453 (2019) - [c74]Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez:
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer. CICC 2019: 1-4 - [c73]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez:
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. CICC 2019: 1-4 - 2018
- [j44]Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. IEEE J. Solid State Circuits 53(3): 799-813 (2018) - [c72]Hamidreza Maghami, Hossein Mirzaie, Pedram Payandehnia, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez:
A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer. MWSCAS 2018: 145-148 - 2017
- [j43]Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu:
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 283-295 (2017) - [c71]Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez:
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. CICC 2017: 1-4 - [c70]Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez:
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC. ISCAS 2017: 1-4 - 2016
- [j42]Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez:
Fast start-up analysis of resonator based oscillators using a power generation method. IET Circuits Devices Syst. 10(5): 357-364 (2016) - [c69]Justin B. Goins, Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez:
JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications. WF-IoT 2016: 48-53 - 2015
- [j41]Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram:
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. IEEE J. Solid State Circuits 50(8): 1833-1847 (2015) - 2014
- [c68]Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez:
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. CICC 2014: 1-4 - [c67]Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks. VLSIC 2014: 1-2 - 2013
- [j40]Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks. IEEE J. Solid State Circuits 48(5): 1250-1263 (2013) - 2012
- [j39]Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez:
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1604-1613 (2012) - [j38]Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez:
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 344-356 (2012) - [c66]Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks. VLSIC 2012: 40-41 - 2011
- [j37]Adam C. Heiberg, Thomas William Brown, Terri S. Fiez, Kartikeya Mayaram:
A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. IEEE J. Solid State Circuits 46(4): 938-949 (2011) - [j36]Thomas William Brown, Farhad Farhabakhshian, Ankur Guha Roy, Terri S. Fiez, Kartikeya Mayaram:
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. IEEE J. Solid State Circuits 46(8): 1782-1795 (2011) - [j35]Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Design-Oriented Analysis of Circuits With Equality Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 1089-1098 (2011) - [j34]Chao Shi, Brian Miller, Kartikeya Mayaram, Terri S. Fiez:
A Multiple-Input Boost Converter for Low-Power Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 827-831 (2011) - [c65]Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez:
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC 2011: 1-4 - 2010
- [j33]James Ayers, Kartikeya Mayaram, Terri S. Fiez:
An Ultralow-Power Receiver for Wireless Sensor Networks. IEEE J. Solid State Circuits 45(9): 1759-1769 (2010) - [c64]Farhad Farhabakhshian, Thomas William Brown, Kartikeya Mayaram, Terri S. Fiez:
A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz. CICC 2010: 1-4
2000 – 2009
- 2009
- [j32]Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. IEEE J. Solid State Circuits 44(2): 427-435 (2009) - [j31]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Automated Design and Optimization of Low-Noise Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 609-622 (2009) - [j30]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Un-Ku Moon, Kartikeya Mayaram:
A Digital PLL With a Stochastic Time-to-Digital Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1612-1621 (2009) - [c63]Wai Leng Cheong, Brian E. Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram:
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. ISQED 2009: 112-115 - 2008
- [j29]Triet Le, Kartikeya Mayaram, Terri S. Fiez:
Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks. IEEE J. Solid State Circuits 43(5): 1287-1302 (2008) - [j28]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity Analysis for Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1521-1534 (2008) - [j27]Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1595-1606 (2008) - [c62]James Ayers, Kartikeya Mayaram, Terri S. Fiez:
A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver. CICC 2008: 591-594 - [c61]Napong Panitantum, Kartikeya Mayaram, Terri S. Fiez:
A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks. CICC 2008: 595-598 - [c60]Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Noise tolerant oscillator design using perturbation projection vector analysis. CICC 2008: 695-698 - [c59]Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Periodic Steady-State Analysis Augmented with Design Equality Constraints. DATE 2008: 312-317 - [c58]Igor Vytyaz, David C. Lee, Un-Ku Moon, Kartikeya Mayaram:
Parameter variation analysis for voltage controlled oscillators in phase-locked loops. ISCAS 2008: 716-719 - 2007
- [j26]Ting Wu, Kartikeya Mayaram, Un-Ku Moon:
An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators. IEEE J. Solid State Circuits 42(4): 775-783 (2007) - [j25]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy. IEEE Trans. Circuits Syst. II Express Briefs 54-II(3): 247-251 (2007) - [c57]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. CICC 2007: 305-308 - [c56]Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram:
Digitally-Enhanced Phase-Locking Circuits. CICC 2007: 361-368 - [c55]Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. CICC 2007: 547-550 - [c54]Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram:
Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits. CICC 2007: 845-848 - [c53]Brett Peterson, Kartikeya Mayaram, Terri S. Fiez:
Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates. CICC 2007: 853-856 - [c52]Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram:
Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency. DAC 2007: 424-429 - [c51]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity analysis for oscillators. ICCAD 2007: 458-463 - [c50]Josh Carnes, Igor Vytyaz, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells. ICECS 2007: 494-497 - [c49]Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram:
Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency. ISCAS 2007: 1073-1076 - [c48]James Ayers, Kartikeya Mayaram, Terri S. Fiez:
Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. ISCAS 2007: 1345-1348 - [c47]Maneesha Yellepeddi, Kartikeya Mayaram:
Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop. ISCAS 2007: 1553-1556 - [c46]Janakiram G. Sankaranarayanan, Kartikeya Mayaram:
Noise Simulation and Modeling for MEMS Varactor Based RF VCOs. ISCAS 2007: 2698-2701 - [c45]Raghuram Jonnalagedda, Kartikeya Mayaram:
Design of Very Low Noise 4.2GHz Clapp VCOs. ISCAS 2007: 2862-2865 - [c44]James Ayers, Kartikeya Mayaram, Terri S. Fiez:
A Low Power BFSK Super-Regenerative Transceiver. ISCAS 2007: 3099-3102 - 2006
- [j24]Kartikeya Mayaram:
CEDA Currents. IEEE Des. Test Comput. 23(2): 168-171 (2006) - [j23]Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram:
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. IEEE J. Solid State Circuits 41(3): 574-587 (2006) - [j22]Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez:
Piezoelectric micro-power generation interface circuits. IEEE J. Solid State Circuits 41(6): 1411-1420 (2006) - [j21]Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning. IEEE J. Solid State Circuits 41(12): 2720-2728 (2006) - [j20]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 932-938 (2006) - [j19]Yutao Hu, Kartikeya Mayaram:
Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2571-2578 (2006) - [j18]Xiaochun Duan, Kartikeya Mayaram:
Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2833-2842 (2006) - [j17]Xiaochun Duan, Kartikeya Mayaram:
Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2843-2851 (2006) - [j16]Patrick Birrer, Sasi Kumar Arunachalam, Martin Held, Kartikeya Mayaram, Terri S. Fiez:
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2578-2587 (2006) - [c43]Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez:
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. CICC 2006: 105-108 - [c42]Triet Le, Kartikeya Mayaram, Terri S. Fiez:
Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks. CICC 2006: 293-296 - [c41]Arathi Sundaresan, Terri S. Fiez, Kartikeya Mayaram:
Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs. CICC 2006: 729-732 - [c40]Ting Wu, Un-Ku Moon, Kartikeya Mayaram:
Dependence of LC VCO oscillation frequency on bias current. ISCAS 2006 - [c39]Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning. ISSCC 2006: 2412-2421 - 2005
- [j15]Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez:
Simulation and measurement of supply and substrate noise in mixed-signal ICs. IEEE J. Solid State Circuits 40(2): 382-391 (2005) - [j14]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
On the numerical stability of Green's function for substrate coupling in integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 653-658 (2005) - [j13]Xiaochun Duan, Kartikeya Mayaram:
An efficient and robust method for ring-oscillator simulation using the harmonic-balance method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1225-1233 (2005) - [j12]Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez:
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 330-338 (2005) - [j11]Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 843-851 (2005) - [c38]Xiaochun Duan, Kartikeya Mayaram:
A new approach for ring oscillator simulation using the harmonic balance method. ASP-DAC 2005: 236-239 - [c37]Xiaochun Duan, Kartikeya Mayaram:
A multiple-probe approach for robust frequency domain ring oscillator simulation. CICC 2005: 465-468 - [c36]Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
A green function-based parasitic extraction method for inhomogeneous substrate layers. DAC 2005: 141-146 - [c35]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
A low spur fractional-N frequency synthesizer architecture. ISCAS (3) 2005: 2807-2810 - [c34]Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. ISCAS (4) 2005: 3986-3989 - [c33]Volodymyr Kratyuk, Igor Vytyaz, Un-Ku Moon, Kartikeya Mayaram:
Analysis of supply and ground noise sensitivity in ring and LC oscillators. ISCAS (6) 2005: 5986-5989 - 2004
- [j10]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(6): 1223-1233 (2004) - [j9]Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-Ku Moon:
Analysis of charge-pump phase-locked loops. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(9): 1665-1674 (2004) - [c32]Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, Chuanjin Richard Shi:
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. ASP-DAC 2004: 163-168 - [c31]Yutao Hu, Kartikeya Mayaram:
A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulation. CICC 2004: 125-128 - [c30]Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram:
Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates. CICC 2004: 367-370 - [c29]Xiaochun Duan, Kartikeya Mayaram:
Frequency domain simulation of high-Q oscillators with homotopy methods. ICCAD 2004: 683-686 - [c28]Ajit Sharma, Chenggang Xu, Wen Kung Chu, Nishath K. Verghese, Terri S. Fiez, Kartikeya Mayaram:
A predictive methodology for accurate substrate parasitic extraction. ISCAS (5) 2004: 149-152 - [c27]Robert Shreeve, Terri S. Fiez, Kartikeya Mayaram:
A physical and analytical model for substrate noise coupling analysis. ISCAS (5) 2004: 157-160 - [c26]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
An improved Z-parameter macro model for substrate noise coupling. ISCAS (5) 2004: 161-164 - [c25]Husni M. Habal, Terri S. Fiez, Kartikeya Mayaram:
An accurate and efficient estimation of switching noise in synchronous digital circuits. ISCAS (2) 2004: 485-488 - [c24]Manas Behera, Volodymyr Kratyuk, Yutao Hu, Kartikeya Mayaram:
Accurate simulation of phase noise in RF MEMS VCOs. ISCAS (3) 2004: 677-680 - [c23]Patrick Birrer, Terri S. Fiez, Kartikeya Mayaram:
Silencer!: a tool for substrate noise coupling analysis. SoCC 2004: 105-108 - 2003
- [c22]Yutao Hu, Kartikeya Mayaram:
A comparison of non-quasi-static and quasi-static harmonic balance implementations for coupled device and circuit simulation. CICC 2003: 99-102 - [c21]Brian E. Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez:
Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits. CICC 2003: 361-364 - [c20]Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez:
Piezoelectric power generation interface circuits. CICC 2003: 489-492 - [c19]Alicia Manthe, Zhao Li, Chuanjin Richard Shi, Kartikeya Mayaram:
Symbolic Analysis of Nonlinear Analog Circuits. DATE 2003: 11108-11109 - [c18]Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
Coupled Simulation of Circuit and Piezoelectric Laminates. ISQED 2003: 369-372 - 2002
- [c17]Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram:
A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes. CICC 2002: 497-500 - [c16]Nathen Barton, Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram:
The effect of supply and substrate noise on jitter in ring oscillators. CICC 2002: 505-508 - [c15]Dicle Ozis, Kartikeya Mayaram, Terri S. Fiez:
An efficient modeling approach for substrate noise coupling analysis. ISCAS (5) 2002: 237-240 - [c14]Yutao Hu, Kartikeya Mayaram:
An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits]. ISCAS (5) 2002: 329-332 - [c13]Nathen Barton, Dicle Özis, Terri S. Fiez, Kartikeya Mayaram:
Analysis of jitter in ring oscillators due to deterministic noise. ISCAS (4) 2002: 393-396 - [c12]N. Seshan, J. Rajagopalan, Kartikeya Mayaram:
Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning range. ISCAS (4) 2002: 409-412 - [c11]Wanliang Ma, Ljiljana Trajkovic, Kartikeya Mayaram:
HomSSPICE: a homotopy-based circuit simulator for periodic steady-state analysis of oscillators. ISCAS (1) 2002: 645-648 - [c10]V. Chandrasekhar, Kartikeya Mayaram:
Analysis of CMOS RF LNAs with ESD protection. ISCAS (4) 2002: 799-802 - 2000
- [j8]Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram, Chenming Hu:
A simple subcircuit extension of the BSIM3v3 model for CMOS RF design. IEEE J. Solid State Circuits 35(4): 612-624 (2000) - [j7]Anil Samavedam, Aline Sadate, Kartikeya Mayaram, Terri S. Fiez:
A scalable substrate noise coupling model for design of mixed-signal IC's. IEEE J. Solid State Circuits 35(6): 895-904 (2000) - [j6]Ruoxin Jiang, Haiming Tang, Kartikeya Mayaram:
A simple and accurate method for calculating the low frequency common-mode gain in a MOS differential amplifier with a current-mirror load. IEEE Trans. Educ. 43(3): 362-364 (2000) - [c9]Oleg Mikulchenko, Kartikeya Mayaram:
Neural Network Design for Behavioral Model Generation with Shape Preserving Properties. BMAS 2000: 97-102
1990 – 1999
- 1999
- [c8]Suet Fong Tin, Kartikeya Mayaram:
Substrate network modeling for CMOS RF circuit simulation. CICC 1999: 583-586 - [c7]Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez:
A scalable substrate noise coupling model for mixed-signal ICs. ICCAD 1999: 128-131 - [c6]Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez:
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes. ISCAS (6) 1999: 218-221 - 1998
- [j5]Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram:
Comments on "A small-signal MOSFET model for radio frequency IC applications". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4): 372-374 (1998) - 1993
- [j4]Richard Burch, Ping Yang, Paul F. Cox, Kartikeya Mayaram:
A new matrix solution technique for general circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2): 225-241 (1993) - [j3]Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang:
Algorithms for transient three-dimensional mixed-level circuit and device simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11): 1726-1733 (1993) - 1992
- [j2]Kartikeya Mayaram, Donald O. Pederson:
Coupling algorithms for mixed-level circuit and device simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 1003-1012 (1992) - 1991
- [c5]Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern:
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications. ICCAD 1991: 112-115 - 1990
- [b1]Donald O. Pederson, Kartikeya Mayaram:
Analog integrated circuits for communication - principles, simulation and design. Kluwer 1990, ISBN 978-0-7923-9089-3, pp. I-XI, 1-568 - [c4]Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern, Richard Burch, Lawrence A. Arledge Jr., Paul F. Cox:
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations. ICCAD 1990: 446-449
1980 – 1989
- 1989
- [c3]Richard Burch, Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang, Paul F. Cox:
PGS and PLUCGS-two new matrix solution techniques for general circuit simulation. ICCAD 1989: 408-411 - 1988
- [j1]Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma:
Techniques for multilayer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 698-712 (1988) - [c2]Kartikeya Mayaram, Donald O. Pederson:
CODECS: a fixed mixed-level device and circuit simulator. ICCAD 1988: 112-115 - 1986
- [c1]Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli:
Chameleon: a new multi-layer channel router. DAC 1986: 495-502
Coauthor Index
[j47] [j46] [j45] [c74] [c73] [j44] [c72] [c71] [c70] [j42] [c69] [j41] [c68] [c67] [j40] [j39] [j38] [c66] [j37] [j36] [j34] [c65] [j33] [c64] [c63] [j29] [j27] [c62] [c61] [c54] [c53] [c48] [c44] [j23] [j22] [j20] [j16] [c43] [c42] [c41] [j15] [j14] [j12] [j11] [c36] [j10] [c30] [c28] [c27] [c26] [c25] [c23] [c21] [c20] [c18] [c17] [c16] [c15] [c13] [j7] [c7] [c6]
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