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ORCIDKazuo Taki
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2000 – 2009
- 2007
[j13]Masao Morimoto, Makoto Nagata
, Kazuo Taki:
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations. IEICE Trans. Electron. 90-C(4): 675-682 (2007)- [j12]Yohei Fukumizu, Naoki Gochi, Makoto Nagata, Kazuo Taki:
A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System. IEICE Trans. Electron. 90-C(6): 1299-1303 (2007) - 2006
- [j11]Yohei Fukumizu, Shuji Ohno, Makoto Nagata, Kazuo Taki:
Communication Scheme for a Highly Collision-Resistive RFID System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 408-415 (2006) - [j10]Yohei Fukumizu, Makoto Nagata, Kazuo Taki:
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach. IEICE Trans. Electron. 89-C(11): 1581-1590 (2006) - [c27]Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki:
A built-in power supply noise probe for digital LSIs. ASP-DAC 2006: 106-107 - 2005
- [j9]Masao Morimoto, Makoto Nagata, Kazuo Taki:
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition. IEICE Trans. Electron. 88-C(10): 2001-2008 (2005) - [j8]Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki:
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3324-3331 (2005) - [j7]Makoto Nagata, Takeshi Okumoto, Kazuo Taki:
A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits. IEEE J. Solid State Circuits 40(4): 813-819 (2005) - 2003
- [j6]Shuusuke Haruna, Norio Sanada, Hisayuki Kinoh, Kazutoshi Sumiya, Kazuo Taki:
A GUI software development system for digital AV applications. Syst. Comput. Jpn. 34(7): 99-107 (2003) - 2002
- [c26]Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto:
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. CICC 2002: 167-170 - 2000
- [c25]Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Yeol Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda:
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. ASP-DAC 2000: 33-34
1990 – 1999
- 1999
- [j5]Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki:
Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits. Syst. Comput. Jpn. 30(7): 55-68 (1999) - 1998
- [c24]Masahiro Yasugi, Shegeyuki Eguchi, Kazuo Taki:
Eliminating Bottlenecks on Parallel Systems using Adaptive Objects. IEEE PACT 1998: 80-87 - [c23]Kazuo Taki:
A Survey for Pass-Transistor Logic Technologies - Recent Researches and Developments and Future Prospects (Embedded Tutorial). ASP-DAC 1998: 223-226 - 1997
- [c22]Kazuo Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi:
Super low power 8-bit CPU with pass-transistor logic. ASP-DAC 1997: 663-664 - [c21]Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki:
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. Asian Test Symposium 1997: 16-21 - 1994
- [j4]Kazuo Taki, Nobuyuki Ichiyoshi:
Parallel processing on the multi-PSI computer and its evaluation - a programming paradigm based on a small-grain highly concurrent object model. Syst. Comput. Jpn. 25(1): 17-36 (1994) - 1992
- [c20]Kazuo Taki:
Parallel Inference Machine PIM. FGCS 1992: 50-72 - [c19]Katsumi Nitta, Kazuo Taki, Nobuyuki Ichiyoshi:
Experimental Parallel Inference Software. FGCS 1992: 166-190 - [c18]Hiroshi Date, Yukinori Matsumoto, Kouichi Kimura, Kazuo Taki, Hiroo Kato, Masahiro Hoshi:
LSI-CAD Programs on Parallel Inference Machine. FGCS 1992: 237-247 - [c17]Keiji Hirata, Reki Yamamoto, Akira Imai, Hideo Kawai, Kiyoshi Hirano, Tsuneyoshi Takagi, Kazuo Taki, Akihiko Nakase, Kazuaki Rokusawa:
Parallel and Distributed Implementation of Concurrent Logic Programming Language KL1. FGCS 1992: 436-459 - [c16]Kazuo Taki:
Towards the General-Purpose Parallel Processing System, Panel Position Paper. FGCS 1992: 1074-1075 - [c15]Yukinori Matsumoto, Kazuo Taki:
Parallel Logic Simulator based on Time Warp and its Evaluation. FGCS 1992: 1198-1206 - 1991
- [c14]Kazuo Taki:
Parallel Programming and Large-scale Applications in the FGCS Project. ICLP 1991: 949 - 1990
- [j3]Yasutaka Takeda, Hiroshi Nakashima, Kanae Masuda, Takashi Chikayama, Kazuo Taki:
A load balancing mechanism for large scale multiprocessor systems and its implementation. New Gener. Comput. 7(2-3): 179-195 (1990) - [c13]Masakazu Furuichi, Kazuo Taki, Nobuyuki Ichiyoshi:
A Multi-Level Load Balancing Scheme for OR-Parallel Exhaustive Search Programs on the Multi-PSI. PPoPP 1990: 50-59
1980 – 1989
- 1989
- [c12]Kazuo Taki:
The FGCS Computing Architecture. IFIP Congress 1989: 627-632 - 1988
- [c11]Kanae Masuda, Hirokazu Ishizuka, Hiroaki Iwayama, Kazuo Taki, Eiji Sugino:
Preliminary Evaluation of the Connection Network for the Multi-PSI System. ECAI 1988: 18-23 - [c10]Shunichi Uchida, Kazuo Taki, Katsuto Nakajima, Atsuhiro Goto, Takashi Chikayama:
Research and Development of the Parallel Inference System in the Intermediate Stage of the FGCS Project. FGCS 1988: 16-36 - [c9]Atsuhiro Goto, Masatoshi Sato, Katsuto Nakajima, Kazuo Taki, Akira Matsumoto:
Overview of the Parallel Inference Machine Architecture (PIM). FGCS 1988: 208-229 - [c8]Yasutaka Takeda, Hiroshi Nakashima, Kanae Masuda, Takashi Chikayama, Kazuo Taki:
A Load Balancing Mechanism for Large Scale Multiprocessor Systems and its Implementation. FGCS 1988: 978-986 - 1987
- [c7]Kazuo Taki, Katsuto Nakajima, Hiroshi Nakashima, Morihiro Ikeda:
Performance and Architectural Evaluation of the PSI Machine. ASPLOS 1987: 128-135 - [c6]M. Ichiyoshi, T. Miyazaki, Kazuo Taki:
A Distributed Implementation of Flat GHC on the Multi-PSI. ICLP 1987: 257-275 - 1986
- [c5]Katsuto Nakajima, Hiroshi Nakashima, Minoru Yokota, Kazuo Taki, Shunichi Uchida, Hiroshi Nishikawa, Akira Yamamoto, Masaki Mitsui:
Evaluation of PSI Micro-Interpreter. COMPCON 1986: 173-177 - 1984
- [c4]Kazuo Taki, Minoru Yokota, Akira Yamamoto, Hiroshi Nishikawa, Shunichi Uchida, Hiroshi Nakashima, Akitoshi Mitsuishi:
Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI). FGCS 1984: 398-409 - [c3]Minoru Yokota, Akira Yamamoto, Kazuo Taki, Hiroshi Nishikawa, Shunichi Uchida, Katsuto Nakajima, Masaki Mitsui:
A Microprogrammed Interpreter for the Personal Sequential Inference Machine. FGCS 1984: 410-418 - 1983
- [j2]Shunichi Uchida, Minoru Yokota, Akira Yamamoto, Kazuo Taki, Hiroshi Nishikawa:
Outline of the Personal Sequential Inference Machine: PSI. New Gener. Comput. 1(1): 75-79 (1983) - [j1]Minoru Yokota, Akira Yamamoto, Kazuo Taki, Hiroshi Nishikawa, Shunichi Uchida:
The Design and Implementation of a Personal Sequential Inference Machine: PSI. New Gener. Comput. 1(2): 125-144 (1983) - [c2]Hiroshi Nishikawa, Minoru Yokota, Akira Yamamoto, Kazuo Taki, Shunichi Uchida:
The Personal Sequential Inference Machine (PSI): Its Design and Machine Architecture. Logic Programming Workshop 1983: 53-73
1970 – 1979
- 1979
- [c1]Kazuo Taki, Yukio Kaneda, Sadao Maekawa:
The Experimental LISP Machine. IJCAI 1979: 865-867
Coauthor Index
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