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2010 – 2019
- 2019
[c39]Tung-Chien Chen, Wei-Ting Wang, Kloze Kao, Chia-Lin Yu, Code Lin, Shu-Hsin Chang, Pei-Kuei Tsung:
NeuroPilot: A Cross-Platform Framework for Edge-AI. AICAS 2019: 167-170- [c38]Pei-Kuei Tsung, Tung-Chien Chen, Chien-Hung Lin, Chih-Yu Chang, Jih-Ming Hsu:
Heterogeneous Computing for Edge AI. VLSI-DAT 2019: 1-2 - 2018
- [c37]Kun-Ying Yeh, Yu-Jie Huang, Tung-Chien Chen, Liang-Gee Chen, Shey-Shi Lu:
A 473 μW wireless 16-channel neural recording SoC with RF energy harvester. VLSI-DAT 2018: 1-4 - 2014
- [c36]Tsung-Chuan Ma, Tung-Chien Chen, Liang-Gee Chen
:
Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem. ICASSP 2014: 3889-3892 - 2013
- [j11]Chung-Te Li, Yen-Chieh Lai, Chien Wu, Sung-Fang Tsai, Tung-Chien Chen, Shao-Yi Chien, Liang-Gee Chen:
Brain-Inspired Framework for Fusion of Multiple Depth Cues. IEEE Trans. Circuits Syst. Video Technol. 23(7): 1137-1149 (2013) - [c35]Li-Fang Cheng, Tung-Chien Chen, Liang-Gee Chen:
Low-power multi-processor system architecture design for universal biomedical signal processing. ISCAS 2013: 857-860 - 2012
- [c34]Hong-Hui Chen, Tung-Chien Chen, Liang-Gee Chen:
Assessing normality of heart sound by matching pursuit residue with frequency-domain-based templates. EMBC 2012: 2917-2920 - [c33]Li-Fang Cheng, Tung-Chien Chen, Liang-Gee Chen:
Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events. EMBC 2012: 4466-4469 - [c32]Tung-Chien Chen, Tsung-Chuan Ma, Yun-Yu Chen, Liang-Gee Chen:
Low power and high accuracy spike sorting microprocessor with on-line interpolation and re-alignment in 90nm CMOS process. EMBC 2012: 4485-4488 - [c31]Nai-Fu Chang, Tung-Chien Chen, Cheng-Yi Chiang, Liang-Gee Chen:
Channel selection for epilepsy seizure prediction method based on machine learning. EMBC 2012: 5162-5165 - [c30]Yun-Yu Chen, Tung-Chien Chen, Chien-Chung Chen, Hsin-I Liao, Luk-Ting Sio, Liang-Gee Chen:
Exploration of reusing the pre-recorded training data set to improve the supervised classifier for EEG-based motor-imagery brain computer interfaces. ISCAS 2012: 2067-2070 - 2011
- [j10]Hong-Hui Chen, Cheng-Yi Chiang, Tung-Chien Chen, Chien-Sheng Liu, Yu-Jie Huang, Shey-Shi Lu, Chii-Wann Lin, Liang-Gee Chen:
Analysis and Design of On-sensor ECG Processors for Realtime Detection of Cardiac Anomalies Including VF, VT, and PVC. J. Signal Process. Syst. 65(2): 275-285 (2011) - [c29]Yu-Hsin Chen, Hong-Hui Chen, Tung-Chien Chen, Liang-Gee Chen:
Robust heart rate measurement with phonocardiogram by on-line template extraction and matching. EMBC 2011: 1957-1960 - [c28]Hong-Hui Chen, Yu-Hsin Chen, Tung-Chien Chen, Liang-Gee Chen:
Mobile energy expenditure tracking system based on heart rate and motion providing extra extensions for personalized care. EMBC 2011: 5256-5259 - [c27]Nai-Fu Chang, Cheng-Yi Chiang, Tung-Chien Chen, Liang-Gee Chen:
Cubic spline interpolation with overlapped window and data reuse for on-line Hilbert Huang transform biomedical microprocessor. EMBC 2011: 7091-7094 - [c26]Cheng-Yi Chiang, Nai-Fu Chang, Tung-Chien Chen, Hong-Hui Chen, Liang-Gee Chen:
Seizure prediction based on classification of EEG synchronization patterns with on-line retraining and post-processing scheme. EMBC 2011: 7564-7569 - [c25]Hong-Hui Chen, Tung-Chien Chen, Cheng-Yi Chiang, Liang-Gee Chen:
Power estimation scheme for lowpower oriented biomedical SoC extended to very deep submicron technology. ICASSP 2011: 749-752 - [c24]Tung-Chien Chen, Yun-Yu Chen, Tsung-Chuan Ma, Liang-Gee Chen:
Design and implementation of cubic spline interpolation for spike sorting microsystems. ICASSP 2011: 1641-1644 - [c23]Pei-Kuei Tsung, Pin-Chih Lin, Kuan-Yu Chen, Tzu-Der Chuang, Hsin-Jung Yang, Shao-Yi Chien, Li-Fu Ding, Wei-Yin Chen, Chih-Chi Cheng, Tung-Chien Chen, Liang-Gee Chen:
A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications. ISSCC 2011: 124-126 - 2010
- [c22]Yun-Yu Chen, Tung-Chien Chen, Liang-Gee Chen:
Accuracy and power tradeoff in spike sorting microsystems with cubic spline interpolation. ISCAS 2010: 1508-1511 - [c21]Yu-Hsin Chen, Tung-Chien Chen, Tsung-Hsueh Lee, Liang-Gee Chen:
Sub-microwatt correlation integral processor for implantable closed-loop epileptic neuromodulator. ISCAS 2010: 2083-2086
2000 – 2009
- 2009
- [j9]Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Liang-Gee Chen:
Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices. IEEE Trans. Circuits Syst. Video Technol. 19(8): 1118-1128 (2009) - [c20]Kuanfu Chen, Tung-Chien Chen, Kimberly Cockerham, Wentai Liu:
Closed-loop Eyelid Reanimation System with Real-time Blink Detection and Electrochemical Stimulation for Facial Nerve Paralysis. ISCAS 2009: 549-552 - [c19]Tung-Chien Chen, Wentai Liu, Liang-Gee Chen:
128-channel Spike Sorting Processor with a Parallel-folding Structure in 90nm Process. ISCAS 2009: 1253-1256 - [c18]Tung-Chien Chen, Kuanfu Chen, Wentai Liu, Liang-Gee Chen:
On-chip Principal Component Analysis with a Mean Pre-estimation Method for Spike Sorting. ISCAS 2009: 3110-3113 - [c17]Li-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Hsu-Kuang Chiu, Yu-Han Chen, Pai-Heng Hsiao, Shao-Yi Chien, Tung-Chien Chen, Ping-Chih Lin, Chia-Yu Chang, Liang-Gee Chen:
A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications. ISSCC 2009: 154-155 - [c16]Tung-Chien Chen, Kuanfu Chen, Zhi Yang, Kimberly Cockerham, Wentai Liu:
A biomedical multiprocessor SoC for closed-loop neuroprosthetic applications. ISSCC 2009: 434-435 - 2008
- [j8]Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sung-Fang Tsai, Liang-Gee Chen:
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder. J. Signal Process. Syst. 50(1): 1-17 (2008) - [j7]Yi-Hau Chen, Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen:
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC. J. Signal Process. Syst. 53(3): 335-347 (2008) - [c15]Moo Sung Chae, Wentai Liu, Zhi Yang, Tung-Chien Chen, Jungsuk Kim, Mohanasankar Sivaprakasam, Mehmet R. Yuce:
A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB Tansmitter. ISSCC 2008: 146-147 - 2007
- [j6]Tung-Chien Chen, Chuan-Yung Tsai, Yu-Wen Huang, Liang-Gee Chen:
Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC. IEEE Trans. Circuits Syst. Video Technol. 17(2): 242-247 (2007) - [j5]Tung-Chien Chen, Yu-Han Chen, Sung-Fang Tsai, Shao-Yi Chien, Liang-Gee Chen:
Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC. IEEE Trans. Circuits Syst. Video Technol. 17(5): 568-577 (2007) - [c14]Chuan-Yuan Tsai, Chen-Han Chung, Yu-Han Chen, Tung-Chien Chen, Liang-Gee Chen:
Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System. ICASSP (2) 2007: 97-100 - [c13]Pei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Shao-Yi Chien, Tung-Chien Chen, Liang-Gee Chen:
System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint. ISCAS 2007: 1001-1004 - [c12]Chung-Jr Lian, Po-Chih Tseng, Tung-Chien Chen, Yu-Wei Chang, Liang-Gee Chen:
Reconfigurable architecture for video applications. SoCC 2007: 21-24 - 2006
- [j4]Ching-Yeh Chen, Shao-Yi Chien, Yu-Wen Huang, Tung-Chien Chen, Tu-Chih Wang, Liang-Gee Chen:
Analysis and architecture design of variable block-size motion estimation for H.264/AVC. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(3): 578-593 (2006) - [j3]Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Bing-Yu Hsieh, Liang-Gee Chen:
Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 832-836 (2006) - [j2]Tung-Chien Chen, Shao-Yi Chien, Yu-Wen Huang, Chen-Han Tsai, Ching-Yeh Chen, To-Wei Chen, Liang-Gee Chen:
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder. IEEE Trans. Circuits Syst. Video Technol. 16(6): 673-688 (2006) - [c11]Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen:
Hardware architecture design of an H.264/AVC video codec. ASP-DAC 2006: 750-757 - [c10]Tung-Chien Chen, Yu-Han Chen, Sung-Fang Tsai, Liang-Gee Chen:
Architecture Design of Low Power Integer Motion Estimation for H. 264/AVC. ICASSP (3) 2006: 900-903 - [c9]Yu-Han Chen, Tung-Chien Chen, Liang-Gee Chen:
Power-Scalable Algorithm and Reconfigurable Macro-Block Pipelining Architecture of H.264 Encoder for Mobile Application. ICME 2006: 281-284 - [c8]Chuan-Yung Tsai, Tung-Chien Chen, Liang-Gee Chen:
Low Power Entropy Coding Hardware Design for H.264/AVC Baseline Profile Encoder. ICME 2006: 1941-1944 - [c7]Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen:
Low power and power aware fractional motion estimation of H.264/AVC for mobile applications. ISCAS 2006 - 2005
- [j1]Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen:
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder. IEEE Trans. Circuits Syst. Video Technol. 15(3): 378-401 (2005) - [c6]Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen:
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. ISCAS (2) 2005: 1790-1793 - [c5]To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, Liang-Gee Chen:
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos. ISCAS (3) 2005: 2931-2934 - 2004
- [c4]Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen:
Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC. ICASSP (5) 2004: 9-12 - [c3]Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen:
Hardware architecture design for H.264/AVC intra frame coder. ISCAS (2) 2004: 269-272 - [c2]Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen:
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. ISCAS (2) 2004: 273-276 - 2003
- [c1]Wei-Min Chao, Tung-Chien Chen, Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen:
Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile. ISCAS (2) 2003: 788-791
Coauthor Index
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