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2020 – today
- 2024
[j30]Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen:
ESEN: Efficient GPU sharing of Ensemble Neural Networks. Neurocomputing 599: 128030 (2024)- [j29]Yasong Cao
, Mei Wen, Zhongdi Luo, Xin Ju, Haolan Huang, Junzhong Shen, Haiyan Chen:
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1590-1601 (2024) - [c79]Yasong Cao, Mei Wen, Junzhong Shen, Zhongxing Li:
BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM. ASAP 2024: 36-44 - [c78]Jing Feng, Mei Wen, Xin Ju, Junzhong Shen, Yang Guo:
Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency. ISCAS 2024: 1-5 - 2023
- [c77]Xiaolei Zhao, Zhaoyun Chen, Yang Shi, Mei Wen, Chunyun Zhang:
Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs. DAC 2023: 1-6 - [c76]Zeyu Xue, Mei Wen, Zhaoyun Chen, Yang Shi, Minjin Tang, Jianchao Yang, Zhongdi Luo:
Releasing the Potential of Tensor Core for Unstructured SpMM using Tiled-CSR Format. ICCD 2023: 457-464 - 2022
- [c75]Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen:
Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling. ASP-DAC 2022: 256-261 - [c74]Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei:
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. HPCC/DSS/SmartCity/DependSys 2022: 126-134 - [c73]Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen:
CORF: Bridging the Gap of Complex Operator Fusion for Faster DNN Inference. HPCC/DSS/SmartCity/DependSys 2022: 1014-1021 - [c72]Jianchao Yang, Mei Wen, Xiaolei Zhao, Yang Shi:
Light: A Component Enhances Faster and More Accurate Traffic Measurement*. ICC 2022: 3673-3678 - [c71]Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang:
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. ICCD 2022: 415-418 - [c70]Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu:
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. ICPP 2022: 18:1-18:11 - [c69]Yuhang Li, Mei Wen, Renyu Yang, Junzhong Shen, Yasong Cao, Jianan Wang:
S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness. ISCAS 2022: 2720-2724 - [c68]Yuhang Li, Mei Wen, Jiawei Fei, Junzhong Shen, Yasong Cao:
TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation. ISPASS 2022: 141-143 - [i4]Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang:
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. CoRR abs/2209.09434 (2022) - 2021
- [j28]Minghua He, Jialiang Qin, Mei Wen, Wenbei Chen:
Sustaining Consumer Trust and Continuance Intention by Institutional Mechanisms: An Empirical Survey of DiDi in China. IEEE Access 9: 158185-158203 (2021) - [c67]Renyu Yang, Junzhong Shen, Mei Wen, Yasong Cao, Yuhang Li:
Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators. HPCC/DSS/SmartCity/DependSys 2021: 133-140 - [c66]Jianchao Yang, Mei Wen, Minjin Tang, Junzhong Shen, Chunyuan Zhang:
SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. HPCC/DSS/SmartCity/DependSys 2021: 1049-1058 - [c65]Yang Shi, Mei Wen:
sRouting: Towards a Better Flow Size Estimation Performance through Routing and Sketch Configuration. ICPP 2021: 65:1-65:11 - [c64]Xiaolei Zhao, Mei Wen, Zhaoyun Chen, Yang Shi, Chunyuan Zhang:
Automatic mapping and code optimization for OpenCL kernels on FT-matrix architecture (WIP paper). LCTES 2021: 37-41 - 2020
- [j27]Zhuang Cao, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang:
P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. IEEE Access 8: 23440-23456 (2020) - [j26]Zhaoyun Chen, Dafei Huang, Lei Luo, Mei Wen, Chunyuan Zhang:
Efficient Parallel TLD on CPU-GPU Platform for Real-Time Tracking. KSII Trans. Internet Inf. Syst. 14(1): 201-220 (2020) - [j25]Junzhong Shen, You Huang, Mei Wen, Chunyuan Zhang:
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1442-1455 (2020) - [j24]Zhaoyun Chen, Wei Quan, Mei Wen, Jianbin Fang, Jie Yu, Chunyuan Zhang, Lei Luo:
Deep Learning Research and Development Platform: Characterizing and Scheduling with QoS Guarantees on GPU Clusters. IEEE Trans. Parallel Distributed Syst. 31(1): 34-50 (2020) - [c63]Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang:
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. DAC 2020: 1-6 - [c62]Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang:
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. FPGA 2020: 315 - [c61]Qixuan Cheng, Mei Wen, Junzhong Shen, Deguang Wang, Chunyuan Zhang:
Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform. ICA3PP (1) 2020: 528-547 - [c60]Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang:
Optimized HybridSketch: More Efficient with Analysis and Algorithm. ICA3PP (1) 2020: 614-626 - [c59]Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang:
HybridSketch: A Memory-centric Precise Approach for Flow Measurement. ICC 2020: 1-7 - [c58]Yang Shi, Mei Wen, Chunyuan Zhang:
Towards High-Efficiency Data Centers via Job-Aware Network Scheduling. ICPP 2020: 19:1-19:10 - [c57]Yang Shi, Mei Wen, Chunyuan Zhang:
Incremental Deployment of Programmable Switches for Sketch-based Network Measurement. ISCC 2020: 1-7
2010 – 2019
- 2019
- [j23]Zijun Hang, Mei Wen, Yang Shi, Chunyuan Zhang:
Interleaved Sketch: Toward Consistent Network Telemetry for Commodity Programmable Switches. IEEE Access 7: 146745-146758 (2019) - [j22]Yang Shi, Jiawei Fei, Mei Wen, Chunyuan Zhang:
Application-Oriented Network Scheduling With Metaflow. IEEE Access 7: 175531-175541 (2019) - [j21]Zhuang Cao, Huiguo Zhang, Junnan Li, Mei Wen, Chunyuan Zhang:
A Fast Approach for Generating Efficient Parsers on FPGAs. Symmetry 11(10): 1265 (2019) - [c56]Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang:
Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. DAC 2019: 207 - [c55]Zhaoyun Chen, Lei Luo, Haoduo Yang, Jie Yu, Mei Wen, Chunyuan Zhang:
GENIE: QoS-guided Dynamic Scheduling for CNN-based Tasks on SME Clusters. DATE 2019: 1599-1602 - [c54]Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang:
Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. FPGA 2019: 117 - [c53]Zijun Hang, Yang Shi, Mei Wen, Wei Quan, Chunyuan Zhang:
SWAP: a sliding window algorithm for in-network packet measurement. HP3C 2019: 84-89 - [c52]Yang Shi, Jiawei Fei, Mei Wen, Qun Huang, Nan Wu:
Metaflow: A Better Traffic Abstraction for Distributed Applications. HPCC/SmartCity/DSS 2019: 1123-1130 - [c51]Zijun Hang, Yang Shi, Mei Wen, Chunyuan Zhang:
TBSW: Time-Based Sliding Window Algorithm for Network Traffic Measurement. HPCC/SmartCity/DSS 2019: 1305-1310 - [c50]Jiawei Fei, Yang Shi, Mei Wen, Chunyuan Zhang:
SACC: Configuring Application-Level Cache Intelligently for In-Memory Database Based on Long Short-Term Memory. HPCC/SmartCity/DSS 2019: 1350-1357 - [c49]Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang:
An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform. ICPP 2019: 98:1-98:10 - [c48]Zhaoyun Chen, Lei Luo, Wei Quan, Mei Wen, Chunyuan Zhang:
Poster Abstract: Deep Learning Workloads Scheduling with Reinforcement Learning on GPU Clusters. INFOCOM Workshops 2019: 1023-1024 - [c47]Zhuang Cao, Huayou Su, Qianming Yang, Mei Wen, Chunyuan Zhang:
Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA. INFOCOM Workshops 2019: 1057-1058 - [c46]Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang:
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. ISCAS 2019: 1-5 - [c45]Yang Shi, Jiawei Fei, Mei Wen, Chunyuan Zhang:
KVSwitch: An In-network Load Balancer for Key-Value Stores. ISCC 2019: 1-7 - [i3]Jiawei Fei, Yang Shi, Qun Huang, Mei Wen:
Metaflow: A DAG-Based Network Abstraction for Distributed Applications. CoRR abs/1901.05571 (2019) - [i2]Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang:
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. CoRR abs/1903.02550 (2019) - 2018
- [j20]You Huang, Junzhong Shen, Yuran Qiao, Mei Wen, Chunyuan Zhang:
MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. IEICE Electron. Express 15(10): 20180286 (2018) - [j19]Haoduo Yang, Huayou Su, Qiang Lan, Mei Wen, Chunyuan Zhang:
HPGraph: High-Performance Graph Analytics with Productivity on the GPU. Sci. Program. 2018: 9340697:1-9340697:11 (2018) - [c44]Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang:
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. FPGA 2018: 97-106 - [c43]Haoduo Yang, Huayou Su, Qiang Lan, Mei Wen, Chunyuan Zhang:
High performance graph analytics with productivity on hybrid CPU-GPU platforms. HP3C 2018: 17-21 - [c42]Zhaoyun Chen, Lei Luo, Wei Quan, Yang Shi, Jie Yu, Mei Wen, Chunyuan Zhang:
Multiple CNN-based Tasks Scheduling across Shared GPU Platform in Research and Development Scenarios. HPCC/SmartCity/DSS 2018: 578-585 - [c41]Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang:
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. ISCAS 2018: 1-5 - [i1]Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang:
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. CoRR abs/1803.03790 (2018) - 2017
- [j18]Qiang Lan, Zelong Wang, Mei Wen, Chunyuan Zhang, Yijie Wang:
High Performance Implementation of 3D Convolutional Neural Networks on a GPU. Comput. Intell. Neurosci. 2017: 8348671:1-8348671:8 (2017) - [j17]Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang:
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. Concurr. Comput. Pract. Exp. 29(20) (2017) - [j16]Dafei Huang, Lei Luo, Zhaoyun Chen, Mei Wen, Chunyuan Zhang:
Applying Detection Proposals to Visual Tracking for Scale and Aspect Ratio Adaptability. Int. J. Comput. Vis. 122(3): 524-541 (2017) - [j15]Zhaoyun Chen, Lei Luo, Dafei Huang, Mei Wen, Chunyuan Zhang:
Exploiting a depth context model in visual tracking with correlation filter. Frontiers Inf. Technol. Electron. Eng. 18(5): 667-679 (2017) - [j14]Yun-gang Xue, Huayou Su, Ju Ren, Mei Wen, Chunyuan Zhang, Li-Quan Xiao:
A Highly Parallel and Scalable Motion Estimation Algorithm with GPU for HEVC. Sci. Program. 2017: 1431574:1-1431574:15 (2017) - [c40]Yanpeng Wang, Mei Wen, Chunyuan Zhang, Jie Lin:
RVNet: A fast and high energy efficiency network packet processing system on RISC-V. ASAP 2017: 107-110 - [c39]Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang:
Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. NPC 2017: 100-111 - 2016
- [c38]Johannes Langguth, Qiang Lan, Namit Gaur, Xing Cai, Mei Wen, Chunyuan Zhang:
Enabling Tissue-Scale Cardiac Simulations Using Heterogeneous Computing on Tianhe-2. ICPADS 2016: 843-852 - 2015
- [j13]Xinnan Dong, Mei Wen, Jun Chai, Xing Cai, Mandan Zhao, Chunyuan Zhang:
Communication-hiding programming for clusters with multi-coprocessor nodes. Concurr. Comput. Pract. Exp. 27(16): 4172-4185 (2015) - [j12]Dafei Huang, Changqing Xun, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai, Qianming Yang:
Enabling a Uniform OpenCL Device View for Heterogeneous Platforms. IEICE Trans. Inf. Syst. 98-D(4): 812-823 (2015) - [j11]Jun Chai, Johan Hake, Nan Wu, Mei Wen, Xing Cai, Glenn Terje Lines, Jing Yang, Huayou Su, Chunyuan Zhang, Xiangke Liao:
Towards simulation of subcellular calcium dynamics at nanometre resolution. Int. J. High Perform. Comput. Appl. 29(1): 51-63 (2015) - [j10]Mei Wen, Dafei Huang, Changqing Xun, Dong Chen:
Improving performance portability for GPU-specific OpenCL kernels on multi-core/many-core CPUs by analysis-based transformations. Frontiers Inf. Technol. Electron. Eng. 16(11): 899-916 (2015) - [j9]Huayou Su, Xing Cai, Mei Wen, Chunyuan Zhang:
An analytical GPU performance model for 3D stencil computations from the angle of data traffic. J. Supercomput. 71(7): 2433-2453 (2015) - [c37]Dafei Huang, Lei Luo, Mei Wen, Zhaoyun Chen, Chunyuan Zhang:
Enable Scale and Aspect Ratio Adaptability in Visual Tracking with Detection Proposals. BMVC 2015: 185.1-185.12 - [c36]Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen:
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. ICA3PP (1) 2015: 64-76 - [c35]Zhaoyun Chen, Lei Luo, Mei Wen, Chunyuan Zhang:
Fast tracking via context depth model learning. ICIP 2015: 4215-4218 - 2014
- [j8]Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai, Chunyuan Zhang:
High efficient sedimentary basin simulations on hybrid CPU-GPU clusters. Clust. Comput. 17(2): 359-369 (2014) - [c34]Dafei Huang, Mei Wen, Changqing Xun, Dong Chen, Xing Cai, Yuran Qiao, Nan Wu, Chunyuan Zhang:
Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs. Euro-Par 2014: 210-221 - [c33]Xinnan Dong, Jun Chai, Jing Yang, Mei Wen, Nan Wu, Xing Cai, Chunyuan Zhang, Zhaoyun Chen:
Utilizing Multiple Xeon Phi Coprocessors on One Compute Node. ICA3PP (2) 2014: 68-81 - 2013
- [j7]Jun Chai, Mei Wen, Nan Wu, Dafei Huang, Jing Yang, Xing Cai, Chunyuan Zhang, Qianming Yang:
Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing. IEICE Trans. Inf. Syst. 96-D(12): 2587-2595 (2013) - [j6]Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang:
Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration. J. Supercomput. 63(2): 508-537 (2013) - [j5]Jun Chai, Huayou Su, Mei Wen, Xing Cai, Nan Wu, Chunyuan Zhang:
Resource-efficient utilization of CPU/GPU-based heterogeneous supercomputers for Bayesian phylogenetic inference. J. Supercomput. 66(1): 364-380 (2013) - [c32]Nan Wu, Yuran Qiao, Mei Wen, Chunyuan Zhang:
ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit. APPT 2013: 319-333 - [c31]Dong Chen, Changqing Xun, Dafei Huang, Mei Wen, Chunyuan Zhang:
Automatic Mapping Single-Device OpenCL Program to Heterogeneous Multi-device Platform. HPCC/EUC 2013: 135-142 - [c30]Jing Yang, Jun Chai, Mei Wen, Nan Wu, Chunyuan Zhang:
Solving the Cardiac Model Using Multi-core CPU and Many Integrated Cores (MIC). HPCC/EUC 2013: 1009-1015 - [c29]Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai:
Performance of Sediment Transport Simulations on NVIDIA's Kepler Architecture. ICCS 2013: 1275-1281 - [c28]Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai:
On the GPU-CPU Performance Portability of OpenCL for 3D Stencil Computations. ICPADS 2013: 78-85 - [c27]Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai:
On the GPU Performance of 3D Stencil Computations Implemented in OpenCL. ISC 2013: 125-135 - 2012
- [c26]Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai, Chunyuan Zhang:
Using 1000+ GPUs and 10000+ CPUs for Sedimentary Basin Simulations. CLUSTER 2012: 27-35 - [c25]Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao:
The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). FPGA 2012: 265 - [c24]Changqing Xun, Mei Wen, Nan Wu, Chunyuan Zhang, Hayden Kwok-Hay So:
Extending BORPH for shared memory reconfigurable computers. FPL 2012: 563-566 - [c23]Huayou Su, Jun Chai, Mei Wen, Ju Ren, Chunyuan Zhang:
Parallelization Design of Irregular Algorithms of Video Processing on GPUs. ICME 2012: 997-1002 - [c22]Nan Wu, Mei Wen, Huayou Su, Ju Ren, Chunyuan Zhang:
A Parallel H.264 Encoder with CUDA: Mapping and Evaluation. ICPADS 2012: 276-283 - [c21]Qiang Lan, Changqing Xun, Mei Wen, Huayou Su, Lifang Liu, Chunyuan Zhang:
Improving Performance of GPU Specific OpenCL Program on CPUs. PDCAT 2012: 356-360 - 2011
- [j4]Xiong Xiong, Mei Wen, Wei Zhang, Yongjie Zhang:
Cross-Market Financial Risk Analysis: an Agent-Based Computational Finance. Int. J. Inf. Technol. Decis. Mak. 10(3): 563-584 (2011) - [j3]Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang:
Tiled Multi-Core Stream Architecture. Trans. High Perform. Embed. Archit. Compil. 4: 274-293 (2011) - [c20]Huayou Su, Nan Wu, Chunyuan Zhang, Mei Wen, Ju Ren:
A Multilevel Parallel Intra Coding for H.264/AVC Based on CUDA. ICIG 2011: 76-81 - [c19]Huayou Su, Chunyuan Zhang, Jun Chai, Mei Wen, Nan Wu, Ju Ren:
High-efficient software parallel CAVLC encoder based on programmable stream processor. ACM Multimedia 2011: 1333-1336 - [c18]Huayou Su, Chunyuan Zhang, Jun Chai, Mei Wen, Nan Wu, Ju Ren:
A high-efficient software parallel CAVCL encoder based on GPU. TSP 2011: 534-540 - 2010
- [c17]Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, Chunyuan Zhang:
SAT: A Stream Architecture Template for Embedded Applications. CIT 2010: 1711-1718 - [c16]Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang:
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. DSD 2010: 823-830 - [c15]Ju Ren, Mei Wen, Chunyuan Zhang, Huayou Su, Yi He, Nan Wu:
A Parallel Streaming Motion Estimation for Real-Time HD H.264 Encoding on Programmable Processors. FCST 2010: 154-160
2000 – 2009
- 2009
- [c14]Ju Ren, Yi He, Wei Wu, Mei Wen, Nan Wu, Chunyuan Zhang:
Software parallel CAVLC encoder based on stream processing. ESTIMedia 2009: 126-133 - [c13]Nan Wu, Mei Wen, Ju Ren, Yi He, Changqing Xun, Wei Wu, Chunyuan Zhang:
Cache streamization for high performance stream processor. HiPC 2009: 140-149 - [c12]Nan Wu, Mei Wen, Wei Wu, Ju Ren, Huayou Su, Changqing Xun, Chunyuan Zhang:
Streaming HD H.264 encoder on programmable processors. ACM Multimedia 2009: 371-380 - 2008
- [j2]Mei Wen, Nan Wu, Chunyuan Zhang, Qianming Yang, Ju Ren, Yi He, Wei Wu, Jun Chai, Maolin Guan, Changqing Xun:
On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator. IEEE Micro 28(4): 51-70 (2008) - [c11]Yi He, Ju Ren, Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang:
FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture. ACSAC 2008: 1-8 - [c10]Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang:
Load scheduling: Reducing pressure on distributed register files for free. ASP-DAC 2008: 340-345 - 2007
- [c9]Nan Wu, Qianming Yang, Mei Wen, Yi He, Changqing Xun, Chunyuan Zhang:
A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision. Asia-Pacific Computer Systems Architecture Conference 2007: 256-267 - [c8]Mei Wen, Nan Wu, Chunyuan Zhang, Wei Wu, Qianming Yang, Changqing Xun:
FT64: Scientific Computing with Streams. HiPC 2007: 209-220 - 2006
- [c7]Mei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang:
Analysis and Performance Results of a fluid dynamics Application on MASA Stream Processor. ACIS-ICIS 2006: 350-354 - [c6]Mei Wen, Nan Wu, Changqing Xun, Wei Wu, Chunyuan Zhang:
Optimization and Evaluating of StreamYGX2 on MASA Stream Processor. Asia-Pacific Computer Systems Architecture Conference 2006: 531-537 - [c5]Nan Wu, Mei Wen, Ju Ren, Yi He, Chunyuan Zhang:
Register Allocation on Stream Processor with Local Register File. Asia-Pacific Computer Systems Architecture Conference 2006: 545-551 - 2005
- [j1]Mei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang:
Multiple-Morphs Adaptive Stream Architecture. J. Comput. Sci. Technol. 20(5): 635-646 (2005) - [c4]Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang:
A Stream Architecture Supporting Multiple Stream Execution Models. Asia-Pacific Computer Systems Architecture Conference 2005: 143-156 - [c3]Haiyan Li, Mei Wen, Chunyuan Zhang, Nan Wu, Li Li, Changqing Xun:
Accelerated Motion Estimation of H.264 on Imagine Stream Processor. ICIAR 2005: 367-374 - 2004
- [c2]Mei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang:
Multiple-Dimension Scalable Adaptive Stream Architecture. Asia-Pacific Computer Systems Architecture Conference 2004: 199-211 - [c1]Mei Wen, Chunyuan Zhang, Nan Wu, Haiyan Li, Li Li:
A Parallel Reed-Solomon Decoder on the Imagine Stream Processor. ISPA 2004: 28-33
Coauthor Index
[c71] [i4] [c66] [c64] [j27] [j26] [j25] [j24] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [j23] [j22] [j21] [c56] [c55] [c54] [c53] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [i2] [j20] [j19] [c44] [c43] [c42] [c41] [i1] [j18] [j17] [j16] [j15] [j14] [c40] [c39] [c38] [j13] [j12] [j11] [j9] [c37] [c35] [j8] [c34] [c33] [j7] [j6] [j5] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [j3] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [j2] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [j1] [c4] [c3] [c2] [c1]
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last updated on 2024-10-07 22:22 CEST by the dblp team
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